Revert "arm: vld1q_types_x3 ACLE intrinsics"

This reverts commit 2514a331835e055a963fd059dc5770e5ae500af0.

4 files changed, 3 insertions, 80 deletions

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index bfad282..1d31777 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -60,69 +60,8 @@ poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a)
     return vld1q_p16_x2 (a);
 }
 
-uint8x16x3_t test_vld1q_u8_x3 (uint8_t * a)
-{
-    return vld1q_u8_x3 (a);
-}
-
-uint16x8x3_t test_vld1q_u16_x3 (uint16_t * a)
-{
-    return vld1q_u16_x3 (a);
-}
-
-uint32x4x3_t test_vld1q_u32_x3 (uint32_t * a)
-{
-    return vld1q_u32_x3 (a);
-}
-
-uint64x2x3_t test_vld1q_u64_x3 (uint64_t * a)
-{
-    return vld1q_u64_x3 (a);
-}
-
-int8x16x3_t test_vld1q_s8_x3 (int8_t * a)
-{
-    return vld1q_s8_x3 (a);
-}
-
-int16x8x3_t test_vld1q_s16_x3 (int16_t * a)
-{
-    return vld1q_s16_x3 (a);
-}
-
-int32x4x3_t test_vld1q_s32_x3 (int32_t * a)
-{
-    return vld1q_s32_x3 (a);
-}
-
-int64x2x3_t test_vld1q_s64_x3 (int64_t * a)
-{
-    return vld1q_s64_x3 (a);
-}
-
-float32x4x3_t test_vld1q_f32_x3 (float32_t * a)
-{
-    return vld1q_f32_x3 (a);
-}
-
-poly8x16x3_t test_vld1q_p8_x3 (poly8_t * a)
-{
-    return vld1q_p8_x3 (a);
-}
-
-poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a)
-{
-    return vld1q_p16_x3 (a);
-}
-
 /* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-
 /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-
 /* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
-
 /* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } }  */
+
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
index 4138fe9..5f6fc98 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
@@ -10,10 +10,4 @@ bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a)
     return vld1q_bf16_x2 (a);
 }
 
-bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a)
-{
-    return vld1q_bf16_x3 (a);
-}
-
 /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
index 01640d7..aecf491 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
@@ -10,10 +10,5 @@ float16x8x2_t test_vld1q_f16_x2 (float16_t * a)
     return vld1q_f16_x2 (a);
 }
 
-float16x8x3_t test_vld1q_f16_x3 (float16_t * a)
-{
-    return vld1q_f16_x3 (a);
-}
-
 /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
+
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
index ae2ab36..04ceb5e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
@@ -10,10 +10,5 @@ poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a)
     return vld1q_p64_x2 (a);
 }
 
-poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a)
-{
-    return vld1q_p64_x3 (a);
-}
-
 /* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
+