aarch64: Improve scalar mode popcount expansion by using SVE [PR113860]

This is similar to the recent improvements to the Advanced SIMD popcount
expansion by using SVE. We can utilize SVE to generate more efficient code for
scalar mode popcount too.

Changes since v1:
* v2: Add a new VNx1BI mode and a new test case for V1DI.
* v3: Abandon VNx1BI changes and add a new variant of aarch64_ptrue_reg.

	PR target/113860

gcc/ChangeLog:

	* config/aarch64/aarch64-protos.h (aarch64_ptrue_reg): New function.
	* config/aarch64/aarch64-simd.md (popcount<mode>2): Update pattern to
	also support V1DI mode.
	* config/aarch64/aarch64.cc (aarch64_ptrue_reg): New function.
	* config/aarch64/aarch64.md (popcount<mode>2): Add TARGET_SVE support.
	* config/aarch64/iterators.md (VDQHSD_V1DI): New mode iterator.
	(SVE_VDQ_I): Add V1DI.
	(bitsize): Likewise.
	(VPRED): Likewise.
	(VEC_POP_MODE): New mode attribute.
	(vec_pop_mode): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/popcnt-sve.c: Update test.
	* gcc.target/aarch64/popcnt11.c: New test.
	* gcc.target/aarch64/popcnt12.c: New test.

Signed-off-by: Pengxuan Zheng <quic_pzheng@quicinc.com>

3 files changed, 83 insertions, 5 deletions

diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c b/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c
index 8e349ef..c3b4c69 100644
--- a/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c
+++ b/gcc/testsuite/gcc.target/aarch64/popcnt-sve.c
@@ -4,7 +4,7 @@
 
 /*
 ** f_v4hi:
-**	ptrue	(p[0-7]).b, all
+**	ptrue	(p[0-7]).b, vl8
 **	ldr	d([0-9]+), \[x0\]
 **	cnt	z\2.h, \1/m, z\2.h
 **	str	d\2, \[x1\]
@@ -21,7 +21,7 @@ f_v4hi (unsigned short *__restrict b, unsigned short *__restrict d)
 
 /*
 ** f_v8hi:
-**	ptrue	(p[0-7]).b, all
+**	ptrue	(p[0-7]).b, vl16
 **	ldr	q([0-9]+), \[x0\]
 **	cnt	z\2.h, \1/m, z\2.h
 **	str	q\2, \[x1\]
@@ -42,7 +42,7 @@ f_v8hi (unsigned short *__restrict b, unsigned short *__restrict d)
 
 /*
 ** f_v2si:
-**	ptrue	(p[0-7]).b, all
+**	ptrue	(p[0-7]).b, vl8
 **	ldr	d([0-9]+), \[x0\]
 **	cnt	z\2.s, \1/m, z\2.s
 **	str	d\2, \[x1\]
@@ -57,7 +57,7 @@ f_v2si (unsigned int *__restrict b, unsigned int *__restrict d)
 
 /*
 ** f_v4si:
-**	ptrue	(p[0-7]).b, all
+**	ptrue	(p[0-7]).b, vl16
 **	ldr	q([0-9]+), \[x0\]
 **	cnt	z\2.s, \1/m, z\2.s
 **	str	q\2, \[x1\]
@@ -74,7 +74,7 @@ f_v4si (unsigned int *__restrict b, unsigned int *__restrict d)
 
 /*
 ** f_v2di:
-**	ptrue	(p[0-7]).b, all
+**	ptrue	(p[0-7]).b, vl16
 **	ldr	q([0-9]+), \[x0\]
 **	cnt	z\2.d, \1/m, z\2.d
 **	str	q\2, \[x1\]
diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt11.c b/gcc/testsuite/gcc.target/aarch64/popcnt11.c
new file mode 100644
index 0000000..e7e67de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/popcnt11.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.2-a+sve" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+/*
+** f_qi:
+**	ldr	b([0-9]+), \[x0\]
+**	cnt	v\1.8b, v\1.8b
+**	smov	w0, v\1.b\[0\]
+**	ret
+*/
+unsigned
+f_qi (unsigned char *a)
+{
+  return __builtin_popcountg (a[0]);
+}
+
+/*
+** f_hi:
+**	ldr	h([0-9]+), \[x0\]
+**	ptrue	(p[0-7]).b, vl8
+**	cnt	z\1.h, \2/m, z\1.h
+**	smov	w0, v\1.h\[0\]
+**	ret
+*/
+unsigned
+f_hi (unsigned short *a)
+{
+  return __builtin_popcountg (a[0]);
+}
+
+/*
+** f_si:
+**	ldr	s([0-9]+), \[x0\]
+**	ptrue	(p[0-7]).b, vl8
+**	cnt	z\1.s, \2/m, z\1.s
+**	umov	x0, v\1.d\[0\]
+**	ret
+*/
+unsigned
+f_si (unsigned int *a)
+{
+  return __builtin_popcountg (a[0]);
+}
+
+/*
+** f_di:
+**	ldr	d([0-9]+), \[x0\]
+**	ptrue	(p[0-7])\.b, vl8
+**	cnt	z\1\.d, \2/m, z\1\.d
+**	fmov	x0, d\1
+**	ret
+*/
+unsigned
+f_di (unsigned long *a)
+{
+  return __builtin_popcountg (a[0]);
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt12.c b/gcc/testsuite/gcc.target/aarch64/popcnt12.c
new file mode 100644
index 0000000..d367ec3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/popcnt12.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fgimple" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */
+
+#pragma GCC target "+nosve"
+
+/*
+** foo:
+**	cnt	(v[0-9]+\.8b), v0\.8b
+**	addv	b0, \1
+**	ret
+*/
+__Uint64x1_t __GIMPLE
+foo (__Uint64x1_t x)
+{
+  __Uint64x1_t z;
+
+  z = .POPCOUNT (x);
+  return z;
+}