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| author | Wilco Dijkstra <wilco.dijkstra@arm.com> | 2024-10-15 16:22:23 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco.dijkstra@arm.com> | 2024-10-23 13:20:01 +0000 |
| commit | 7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9 (patch) | |
| tree | 61d52891bf10fa7a9f2d693fdc8a8aabd65b1d4f /gcc/testsuite | |
| parent | 2b666dc4d1c96e0ea3597fe7e502a70198a66c03 (diff) | |
| download | gcc-7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9.zip gcc-7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9.tar.gz gcc-7c7c895c2f34d2a5c0cd2139c5e76c13c6c030c9.tar.bz2 | |
AArch64: Fix copysign patterns
The current copysign pattern has a mismatch in the predicates and constraints -
operand[2] is a register_operand but also has an alternative X which allows any
operand. Since it is a floating point operation, having an integer alternative
makes no sense. Change the expander to always use vector immediates which
results in better code and sharing of immediates between copysign and xorsign.
gcc/ChangeLog:
* config/aarch64/aarch64.md (copysign<GPF:mode>3): Widen immediate to
vector.
(copysign<GPF:mode>3_insn): Use VQ_INT_EQUIV in operand 3.
* config/aarch64/iterators.md (VQ_INT_EQUIV): New iterator.
(vq_int_equiv): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/copysign_3.c: New test.
* gcc.target/aarch64/copysign_4.c: New test.
* gcc.target/aarch64/fneg-abs_2.c: Fixup test.
* gcc.target/aarch64/sve/fneg-abs_2.c: Likewise.
Diffstat (limited to 'gcc/testsuite')
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/copysign_3.c | 16 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/copysign_4.c | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c | 2 |
4 files changed, 35 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/copysign_3.c b/gcc/testsuite/gcc.target/aarch64/copysign_3.c new file mode 100644 index 0000000..be48682 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/copysign_3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +float f1 (float x, float y) +{ + return __builtin_copysignf (1.0, x) * __builtin_copysignf (1.0, y); +} + +double f2 (double x, double y) +{ + return __builtin_copysign (1.0, x) * __builtin_copysign (1.0, y); +} + +/* { dg-final { scan-assembler-times "movi\t" 2 } } */ +/* { dg-final { scan-assembler-not "copysign\tw" } } */ +/* { dg-final { scan-assembler-not "dup\tw" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/copysign_4.c b/gcc/testsuite/gcc.target/aarch64/copysign_4.c new file mode 100644 index 0000000..f3cec2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/copysign_4.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a+sve" } */ + +float f1 (float x, float y) +{ + return __builtin_copysignf (1.0, x) * __builtin_copysignf (1.0, y); +} + +double f2 (double x, double y) +{ + return __builtin_copysign (1.0, x) * __builtin_copysign (1.0, y); +} + +/* { dg-final { scan-assembler-times "movi\t" 1 } } */ +/* { dg-final { scan-assembler-times "mov\tz" 1 } } */ +/* { dg-final { scan-assembler-not "copysign\tw" } } */ +/* { dg-final { scan-assembler-not "dup\tw" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c index 18d10ee..9fe8e9b 100644 --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c @@ -9,7 +9,7 @@ /* ** f1: -** orr v[0-9]+.2s, #?128, lsl #?24 +** orr v[0-9]+.4s, #?128, lsl #?24 ** ret */ float32_t f1 (float32_t a) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c index fe08fe3..cc97c95 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c @@ -7,7 +7,7 @@ /* ** f1: -** orr v0.2s, #?128, lsl #?24 +** orr v0.4s, #?128, lsl #?24 ** ret */ float32_t f1 (float32_t a) |