config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Check for vector...

config/rs6000/rs6000.c (rs6000_legitimize_reload_address): Check for
vector types if to use base reg for misaligned non-word ld/std.
OKed by David Edelsohn.

From-SVN: r95529

1 files changed, 23 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.dg/altivec-20.c b/gcc/testsuite/gcc.dg/altivec-20.c
new file mode 100644
index 0000000..f733d18
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/altivec-20.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-maltivec -mcpu=G5 -O2" } */
+
+#include <altivec.h>
+
+void foo( float scalar)
+{
+    unsigned long width;
+    unsigned long x;
+    vector float vColor;
+    vector unsigned int selectMask;
+    vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) );
+
+    float *destRow;
+    vector float store, load0;
+
+    for( ; x < width; x++)
+    {
+            load0 = vec_sel( vColor, load0, selectMask );
+            vec_st( store, 0, destRow );
+            store = load0;
+    }
+}