re PR target/24230 (ICE in extract_insn with altivec)

2005-11-07  Paolo Bonzini  <bonzini@gnu.org>

	PR target/24230

	* config/rs6000/rs6000.c (easy_vector_splat_const, easy_vector_same,
	gen_easy_vector_constant_add_self): Delete.
	(vspltis_constant, easy_altivec_constant, gen_easy_altivec_constant):
	New.
	(output_vec_const_move): Use gen_easy_altivec_constant.
	(rs6000_expand_vector_init): Do not emit a set of a VEC_DUPLICATE.
	* config/rs6000/predicates.md (easy_vector_constant): Reorganize tests.
	(easy_vector_constant_add_self): Rewritten.
	* config/rs6000/rs6000-protos.h (easy_vector_splat_const,
	easy_vector_same, gen_easy_vector_constant_add_self): Remove prototype.
	(easy_altivec_constant, gen_easy_altivec_constant): Add prototype.

testsuite:
2005-11-07  Paolo Bonzini  <bonzini@gnu.org>

	PR target/24230

        * gcc.target/powerpc/altivec-consts.c,
        gcc.target/powerpc/altivec-splat.c: New testcase.

From-SVN: r106588

3 files changed, 377 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index befbe80..53cb481 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,14 @@
 2005-11-07  Paolo Bonzini  <bonzini@gnu.org>
 
+	PR target/24230
+
+        * gcc.target/powerpc/altivec-consts.c,
+        gcc.target/powerpc/altivec-splat.c: New testcase.
+
+2005-11-07  Paolo Bonzini  <bonzini@gnu.org>
+
+	PR c/24599
+
         * gcc.dg/overflow-2.c: New testcase.
 
 2005-11-07  Jakub Jelinek  <jakub@redhat.com>
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-consts.c b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
new file mode 100644
index 0000000..2bea323
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
@@ -0,0 +1,320 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Check that "easy" AltiVec constants are correctly synthesized.  */
+
+#include "altivec_check.h"
+
+extern void abort (void);
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+char w[16] __attribute__((aligned(16)));
+ 
+
+/* Emulate the vspltis? instructions on a 16-byte array of chars.  */
+
+void vspltisb (char *v, char val)
+{
+  int i;
+  for (i = 0; i < 16; i++)
+    v[i] = val;
+}
+
+void vspltish (char *v, char val)
+{
+  int i;
+  for (i = 0; i < 16; i += 2)
+    v[i] = val >> 7, v[i + 1] = val;
+}
+
+void vspltisw (char *v, char val)
+{
+  int i;
+  for (i = 0; i < 16; i += 4)
+    v[i] = v[i + 1] = v[i + 2] = val >> 7, v[i + 3] = val;
+}
+
+
+/* Use three different check functions for each mode-instruction pair.
+   The callers have no typecasting and no addressable vectors, to make
+   the test more robust.  */
+
+void __attribute__ ((noinline)) check_v16qi (v16qi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v8hi (v8hi v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+void __attribute__ ((noinline)) check_v4si (v4si v1, char *v2)
+{
+  if (memcmp (&v1, v2, 16))
+    abort ();
+}
+
+
+/* V16QI tests.  */
+
+void v16qi_vspltisb ()
+{
+  v16qi v = { 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15 };
+  vspltisb (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_neg ()
+{
+  v16qi v = { -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5, -5 };
+  vspltisb (w, -5);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_addself ()
+{
+  v16qi v = { 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30, 30 };
+  vspltisb (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisb_neg_addself ()
+{
+  v16qi v = { -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24, -24 };
+  vspltisb (w, -24);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish ()
+{
+  v16qi v = { 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15, 0, 15 };
+  vspltish (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish_addself ()
+{
+  v16qi v = { 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30, 0, 30 };
+  vspltish (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltish_neg ()
+{
+  v16qi v = { -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5, -1, -5 };
+  vspltish (w, -5);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw ()
+{
+  v16qi v = { 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15, 0, 0, 0, 15 };
+  vspltisw (w, 15);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw_addself ()
+{
+  v16qi v = { 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30, 0, 0, 0, 30 };
+  vspltisw (w, 30);
+  check_v16qi (v, w);
+}
+
+void v16qi_vspltisw_neg ()
+{
+  v16qi v = { -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5, -1, -1, -1, -5 };
+  vspltisw (w, -5);
+  check_v16qi (v, w);
+}
+
+
+/* V8HI tests. */
+
+void v8hi_vspltisb ()
+{
+  v8hi v = { 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F, 0x0F0F };
+  vspltisb (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisb_addself ()
+{
+  v8hi v = { 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E, 0x1E1E };
+  vspltisb (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisb_neg ()
+{
+  v8hi v = { 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB, 0xFBFB };
+  vspltisb (w, -5);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish ()
+{
+  v8hi v = { 15, 15, 15, 15, 15, 15, 15, 15 };
+  vspltish (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_neg ()
+{
+  v8hi v = { -5, -5, -5, -5, -5, -5, -5, -5 };
+  vspltish (w, -5);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_addself ()
+{
+  v8hi v = { 30, 30, 30, 30, 30, 30, 30, 30 };
+  vspltish (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltish_neg_addself ()
+{
+  v8hi v = { -24, -24, -24, -24, -24, -24, -24, -24 };
+  vspltish (w, -24);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw ()
+{
+  v8hi v = { 0, 15, 0, 15, 0, 15, 0, 15 };
+  vspltisw (w, 15);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw_addself ()
+{
+  v8hi v = { 0, 30, 0, 30, 0, 30, 0, 30 };
+  vspltisw (w, 30);
+  check_v8hi (v, w);
+}
+
+void v8hi_vspltisw_neg ()
+{
+  v8hi v = { -1, -5, -1, -5, -1, -5, -1, -5 };
+  vspltisw (w, -5);
+  check_v8hi (v, w);
+}
+
+/* V4SI tests. */
+
+void v4si_vspltisb ()
+{
+  v4si v = { 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F };
+  vspltisb (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisb_addself ()
+{
+  v4si v = { 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E, 0x1E1E1E1E };
+  vspltisb (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisb_neg ()
+{
+  v4si v = { 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB, 0xFBFBFBFB };
+  vspltisb (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish ()
+{
+  v4si v = { 0x000F000F, 0x000F000F, 0x000F000F, 0x000F000F };
+  vspltish (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish_addself ()
+{
+  v4si v = { 0x001E001E, 0x001E001E, 0x001E001E, 0x001E001E };
+  vspltish (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltish_neg ()
+{
+  v4si v = { 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB, 0xFFFBFFFB };
+  vspltish (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw ()
+{
+  v4si v = { 15, 15, 15, 15 };
+  vspltisw (w, 15);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_neg ()
+{
+  v4si v = { -5, -5, -5, -5 };
+  vspltisw (w, -5);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_addself ()
+{
+  v4si v = { 30, 30, 30, 30 };
+  vspltisw (w, 30);
+  check_v4si (v, w);
+}
+
+void v4si_vspltisw_neg_addself ()
+{
+  v4si v = { -24, -24, -24, -24 };
+  vspltisw (w, -24);
+  check_v4si (v, w);
+}
+
+
+
+int main ()
+{
+  altivec_check ();   /* Exit if hardware doesn't support AltiVec.  */
+
+  v16qi_vspltisb ();
+  v16qi_vspltisb_neg ();
+  v16qi_vspltisb_addself ();
+  v16qi_vspltisb_neg_addself ();
+  v16qi_vspltish ();
+  v16qi_vspltish_addself ();
+  v16qi_vspltish_neg ();
+  v16qi_vspltisw ();
+  v16qi_vspltisw_addself ();
+  v16qi_vspltisw_neg ();
+
+  v8hi_vspltisb ();
+  v8hi_vspltisb_addself ();
+  v8hi_vspltisb_neg ();
+  v8hi_vspltish ();
+  v8hi_vspltish_neg ();
+  v8hi_vspltish_addself ();
+  v8hi_vspltish_neg_addself ();
+  v8hi_vspltisw ();
+  v8hi_vspltisw_addself ();
+  v8hi_vspltisw_neg ();
+
+  v4si_vspltisb ();
+  v4si_vspltisb_addself ();
+  v4si_vspltisb_neg ();
+  v4si_vspltish ();
+  v4si_vspltish_addself ();
+  v4si_vspltish_neg ();
+  v4si_vspltisw ();
+  v4si_vspltisw_neg ();
+  v4si_vspltisw_addself ();
+  v4si_vspltisw_neg_addself ();
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-splat.c b/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
new file mode 100644
index 0000000..7e2471fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-splat.c
@@ -0,0 +1,48 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-options "-maltivec -mabi=altivec -O2" } */
+
+/* Testcase by Richard Guenther and Steven Bosscher.
+   Check that "easy" AltiVec constants are correctly synthesized
+   if they need to be reloaded.  */
+
+typedef __attribute__ ((vector_size (16))) unsigned char v16qi;
+typedef __attribute__ ((vector_size (16))) unsigned short v8hi;
+typedef __attribute__ ((vector_size (16))) unsigned int v4si;
+
+#define REGLIST								\
+  "77",  "78",  "79",  "80",  "81",  "82",  "83",  "84",  "85",  "86",	\
+  "87",  "88",  "89",  "90",  "91",  "92",  "93",  "94",  "95",  "96",	\
+  "97",  "98",  "99", "100", "101", "102", "103", "104", "105", "106",	\
+ "107", "108"
+
+
+#define TEST(a, result, b)				\
+  void a##_##b (int h)					\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (5);	\
+      }							\
+  }							\
+							\
+  void a##_##b##_neg (int h)				\
+  {							\
+    volatile a tmp;					\
+    while (h-- > 0)					\
+      {							\
+        asm ("" : : : REGLIST);				\
+        tmp = (a) (result) __builtin_altivec_##b (-5);	\
+      }							\
+  }
+
+TEST(v16qi, v16qi, vspltisb)
+TEST(v16qi, v8hi, vspltish)
+TEST(v16qi, v4si, vspltisw)
+TEST(v8hi, v16qi, vspltisb)
+TEST(v8hi, v8hi, vspltish)
+TEST(v8hi, v4si, vspltisw)
+TEST(v4si, v16qi, vspltisb)
+TEST(v4si, v8hi, vspltish)
+TEST(v4si, v4si, vspltisw)