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| author | GCC Administrator <gccadmin@gcc.gnu.org> | 2025-08-23 00:17:47 +0000 |
|---|---|---|
| committer | GCC Administrator <gccadmin@gcc.gnu.org> | 2025-08-23 00:17:47 +0000 |
| commit | 64d9e5ab61e55c63e7ebaf9754af0564ea09a76b (patch) | |
| tree | 33d38ec151544ff65cbc0e288b87b5e9930603b0 /gcc/testsuite | |
| parent | 9d63110c4334335a920424c301691dae9ecf398f (diff) | |
| download | gcc-64d9e5ab61e55c63e7ebaf9754af0564ea09a76b.zip gcc-64d9e5ab61e55c63e7ebaf9754af0564ea09a76b.tar.gz gcc-64d9e5ab61e55c63e7ebaf9754af0564ea09a76b.tar.bz2 | |
Daily bump.
Diffstat (limited to 'gcc/testsuite')
| -rw-r--r-- | gcc/testsuite/ChangeLog | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index edd9640..b28c221 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,63 @@ +2025-08-22 Jeff Law <jlaw@ventanamicro.com> + + PR rtl-optimization/120553 + * gcc.target/riscv/pr120553-1.c: New test. + * gcc.target/riscv/pr120553-2.c: New test. + * gcc.target/riscv/pr120553-3.c: New test. + * gcc.target/riscv/pr120553-4.c: New test. + * gcc.target/riscv/pr120553-5.c: New test. + * gcc.target/riscv/pr120553-6.c: New test. + * gcc.target/riscv/pr120553-7.c: New test. + * gcc.target/riscv/pr120553-8.c: New test. + +2025-08-22 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. + * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u16-from-u64.rv32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u32-from-u64.rv32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u64-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-4-u8-from-u64.rv32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u16-from-u64.rv32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u32-from-u64.rv32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u64-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u128.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u16.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u32.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.c: New test. + * gcc.target/riscv/sat/sat_u_mul-run-4-u8-from-u64.rv32.c: New test. + +2025-08-22 H.J. Lu <hjl.tools@gmail.com> + + PR target/121635 + * gcc.target/i386/pr121635-1a.c: New test. + * gcc.target/i386/pr121635-1b.c: Likewise. + +2025-08-22 Nathaniel Shead <nathanieloshead@gmail.com> + + * g++.dg/abi/mangle83.C: Disable implicit enum test for + -fshort-enums. + +2025-08-22 Alexandre Oliva <oliva@adacore.com> + + PR rtl-optimization/120424 + * lib/target-supports.exp (arm arches): Add arm_arch_v7. + * g++.target/arm/pr120424.C: Require armv7 support. Use + dg-add-options arm_arch_v7 instead of explicit -march=armv7. + 2025-08-21 Steven G. Kargl <kargl@gcc.gnu.org> PR fortran/121627 |