i386.md (isa): Add x64_avx512dq, enable if TARGET_64BIT && TARGET_AVX512DQ.

	* config/i386/i386.md (isa): Add x64_avx512dq, enable if
	TARGET_64BIT && TARGET_AVX512DQ.
	* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
	(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
	(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
	*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
	(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
	(*vec_extractv4si_zext): Add avx512dq alternative.
	(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
	use v instead of x constraint in other alternatives where possible.

	* gcc.target/i386/avx512bw-vpextr-1.c: New test.
	* gcc.target/i386/avx512dq-vpextr-1.c: New test.

From-SVN: r236167

3 files changed, 165 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index d893b58..f4f2390 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2016-05-12  Jakub Jelinek  <jakub@redhat.com>
 
+	* gcc.target/i386/avx512bw-vpextr-1.c: New test.
+	* gcc.target/i386/avx512dq-vpextr-1.c: New test.
+
 	* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
 	* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
 	* gcc.target/i386/avx512vl-vpinsr-1.c: New test.
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpextr-1.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpextr-1.c
new file mode 100644
index 0000000..f4eea9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpextr-1.c
@@ -0,0 +1,109 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+
+typedef char v16qi __attribute__((vector_size (16)));
+typedef short v8hi __attribute__((vector_size (16)));
+typedef int v4si __attribute__((vector_size (16)));
+typedef long long v2di __attribute__((vector_size (16)));
+
+void
+f1 (v16qi a)
+{
+  register v16qi c __asm ("xmm16") = a;
+  register unsigned char e __asm ("dl");
+  asm volatile ("" : "+v" (c));
+  v16qi d = c;
+  e = ((unsigned char *) &d)[3];
+  asm volatile ("" : : "q" (e));
+}
+
+unsigned short
+f2 (v8hi a)
+{
+  register v8hi c __asm ("xmm16") = a;
+  register unsigned short e __asm ("dx");
+  asm volatile ("" : "+v" (c));
+  v8hi d = c;
+  e = ((unsigned short *) &d)[3];
+  asm volatile ("" : : "r" (e));
+}
+
+unsigned int
+f3 (v16qi a)
+{
+  register v16qi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v16qi d = c;
+  return ((unsigned char *) &d)[3];
+}
+
+unsigned int
+f4 (v8hi a)
+{
+  register v8hi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v8hi d = c;
+  return ((unsigned short *) &d)[3];
+}
+
+unsigned long long
+f5 (v16qi a)
+{
+  register v16qi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v16qi d = c;
+  return ((unsigned char *) &d)[3];
+}
+
+unsigned long long
+f6 (v8hi a)
+{
+  register v8hi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v8hi d = c;
+  return ((unsigned short *) &d)[3];
+}
+
+void
+f7 (v16qi a, unsigned char *p)
+{
+  register v16qi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v16qi d = c;
+  *p = ((unsigned char *) &d)[3];
+}
+
+void
+f8 (v8hi a, unsigned short *p)
+{
+  register v8hi c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v8hi d = c;
+  *p = ((unsigned short *) &d)[3];
+}
+
+void
+f9 (v4si a)
+{
+  register v4si c __asm ("xmm16") = a;
+  register unsigned int e __asm ("xmm17");
+  asm volatile ("" : "+v" (c));
+  v4si d = c;
+  e = ((unsigned int *) &d)[3];
+  asm volatile ("" : "+v" (e));
+}
+
+void
+f10 (v2di a)
+{
+  register v2di c __asm ("xmm16") = a;
+  register unsigned long long e __asm ("xmm17");
+  asm volatile ("" : "+v" (c));
+  v2di d = c;
+  e = ((unsigned long long *) &d)[1];
+  asm volatile ("" : "+v" (e));
+}
+
+/* { dg-final { scan-assembler-times "vpextrb\[^\n\r]*xmm16" 4 } } */
+/* { dg-final { scan-assembler-times "vpextrw\[^\n\r]*xmm16" 4 } } */
+/* { dg-final { scan-assembler-times "vpsrldq\[^\n\r]*xmm1\[67\]\[^\n\r]*xmm1\[67\]" 2 } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vpextr-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vpextr-1.c
new file mode 100644
index 0000000..3c6abaf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512dq-vpextr-1.c
@@ -0,0 +1,53 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512dq" } */
+
+typedef int v4si __attribute__((vector_size (16)));
+typedef long long v2di __attribute__((vector_size (16)));
+
+unsigned int
+f1 (v4si a)
+{
+  register v4si c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v4si d = c;
+  return ((unsigned int *) &d)[3];
+}
+
+unsigned long long
+f2 (v2di a)
+{
+  register v2di c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v2di d = c;
+  return ((unsigned long long *) &d)[1];
+}
+
+unsigned long long
+f3 (v4si a)
+{
+  register v4si c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v4si d = c;
+  return ((unsigned int *) &d)[3];
+}
+
+void
+f4 (v4si a, unsigned int *p)
+{
+  register v4si c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v4si d = c;
+  *p = ((unsigned int *) &d)[3];
+}
+
+void
+f5 (v2di a, unsigned long long *p)
+{
+  register v2di c __asm ("xmm16") = a;
+  asm volatile ("" : "+v" (c));
+  v2di d = c;
+  *p = ((unsigned long long *) &d)[1];
+}
+
+/* { dg-final { scan-assembler-times "vpextrd\[^\n\r]*xmm16" 3 } } */
+/* { dg-final { scan-assembler-times "vpextrq\[^\n\r]*xmm16" 2 } } */