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authorEzra Sitorus <ezra.sitorus@arm.com>2023-12-07 15:28:44 +0000
committerRichard Earnshaw <rearnsha@arm.com>2023-12-07 17:14:40 +0000
commit2f48d846c794ba091b266133f73717361096d454 (patch)
treef444f00a63186e377059f13ee24492826f6c271f /gcc/testsuite
parentef07ae652c25ec04c2e3ef8cec14b0771a809861 (diff)
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arm: vst1_types_x4 ACLE intrinsics
This patch is part of a series of patches implementing the _xN variants of the vst1 intrinsic for the arm port. This patch adds the _x4 variants of the vst1 intrinsic. ACLE documents: https://developer.arm.com/documentation/ihi0053/latest/ ISA documents: https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New. (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New. (vst1_f16_x4, vst1_f32_x4): New. (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New. (vst1_bf16_x4): New. * config/arm/arm_neon_builtins.def (vst1_x4): New entries. * config/arm/neon.md (vst1_x4<mode>): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1_base_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_bf16_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_fp16_xN_1.c: Add new test. * gcc.target/arm/simd/vst1_p64_xN_1.c: Add new test.
Diffstat (limited to 'gcc/testsuite')
-rw-r--r--gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c62
-rw-r--r--gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c6
-rw-r--r--gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c7
-rw-r--r--gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c7
4 files changed, 75 insertions, 7 deletions
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
index 5f820a6..04ca6583 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_base_xN_1.c
@@ -115,8 +115,62 @@ void test_vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)
vst1_p16_x3 (ptr, val);
}
+void test_vst1_u8_x4 (uint8_t * ptr, uint8x8x4_t val)
+{
+ vst1_u8_x4 (ptr, val);
+}
+
+void test_vst1_u16_x4 (uint16_t * ptr, uint16x4x4_t val)
+{
+ vst1_u16_x4 (ptr, val);
+}
+
+void test_vst1_u32_x4 (uint32_t * ptr, uint32x2x4_t val)
+{
+ vst1_u32_x4 (ptr, val);
+}
+
+void test_vst1_u64_x4 (uint64_t * ptr, uint64x1x4_t val)
+{
+ vst1_u64_x4 (ptr, val);
+}
+
+void test_vst1_s8_x4 (int8_t * ptr, int8x8x4_t val)
+{
+ vst1_s8_x4 (ptr, val);
+}
+
+void test_vst1_s16_x4 (int16_t * ptr, int16x4x4_t val)
+{
+ vst1_s16_x4 (ptr, val);
+}
+
+void test_vst1_s32_x4 (int32_t * ptr, int32x2x4_t val)
+{
+ vst1_s32_x4 (ptr, val);
+}
+
+void test_vst1_s64_x4 (int64_t * ptr, int64x1x4_t val)
+{
+ vst1_s64_x4 (ptr, val);
+}
+
+void test_vst1_f32_x4 (float32_t * ptr, float32x2x4_t val)
+{
+ vst1_f32_x4 (ptr, val);
+}
+
+void test_vst1_p8_x4 (poly8_t * ptr, poly8x8x4_t val)
+{
+ vst1_p8_x4 (ptr, val);
+}
+
+void test_vst1_p16_x4 (poly16_t * ptr, poly16x4x4_t val)
+{
+ vst1_p16_x4 (ptr, val);
+}
-/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 9 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 6 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
index a3a00ea..d919c7d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_bf16_xN_1.c
@@ -15,4 +15,8 @@ void test_vst1_bf16_x3 (bfloat16_t * ptr, bfloat16x4x3_t val)
vst1_bf16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+void test_vst1_bf16_x4 (bfloat16_t * ptr, bfloat16x4x4_t val)
+{
+ vst1_bf16_x4 (ptr, val);
+}
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
index 0a6863e..3d1d1eb7 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_fp16_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)
vst1_f16_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
+void test_vst1_f16_x4 (float16_t * ptr, float16x4x4_t val)
+{
+ vst1_f16_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
index 5dbd604..6291214 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1_p64_xN_1.c
@@ -15,4 +15,9 @@ void test_vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)
vst1_p64_x3 (ptr, val);
}
-/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file
+void test_vst1_p64_x4 (poly64_t * ptr, poly64x1x4_t val)
+{
+ vst1_p64_x4 (ptr, val);
+}
+
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 3 } } */ \ No newline at end of file