arm: vld1q_types_x3 ACLE intrinsics

This patch is part of a series of patches implementing the _xN
variants of the vld1q intrinsic for the arm port. This patch adds the
_x3 variants of the vld1q intrinsic.

ACLE documents:
https://developer.arm.com/documentation/ihi0053/latest/

ISA documents:
https://developer.arm.com/documentation/ddi0487/latest/

gcc/ChangeLog:
	* config/arm/arm_neon.h
	(vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
	(vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
	(vld1q_f16_x3, vld1q_f32_x3): New.
	(vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
	(vld1q_bf16_x3): New.
	* config/arm/arm_neon_builtins.def (vld1_x3): New entries.
	* config/arm/neon.md (vld1_x3<mode>): New.

gcc/testsuite/ChangeLog:
	* gcc.target/arm/simd/vld1q_base_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1q_bf16_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1q_fp16_xN_1.c: Add new tests.
	* gcc.target/arm/simd/vld1q_p64_xN_1.c: Add new tests.

4 files changed, 80 insertions, 3 deletions

diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
index 1d31777..bfad282 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_base_xN_1.c
@@ -60,8 +60,69 @@ poly16x8x2_t test_vld1q_p16_x2 (poly16_t * a)
     return vld1q_p16_x2 (a);
 }
 
+uint8x16x3_t test_vld1q_u8_x3 (uint8_t * a)
+{
+    return vld1q_u8_x3 (a);
+}
+
+uint16x8x3_t test_vld1q_u16_x3 (uint16_t * a)
+{
+    return vld1q_u16_x3 (a);
+}
+
+uint32x4x3_t test_vld1q_u32_x3 (uint32_t * a)
+{
+    return vld1q_u32_x3 (a);
+}
+
+uint64x2x3_t test_vld1q_u64_x3 (uint64_t * a)
+{
+    return vld1q_u64_x3 (a);
+}
+
+int8x16x3_t test_vld1q_s8_x3 (int8_t * a)
+{
+    return vld1q_s8_x3 (a);
+}
+
+int16x8x3_t test_vld1q_s16_x3 (int16_t * a)
+{
+    return vld1q_s16_x3 (a);
+}
+
+int32x4x3_t test_vld1q_s32_x3 (int32_t * a)
+{
+    return vld1q_s32_x3 (a);
+}
+
+int64x2x3_t test_vld1q_s64_x3 (int64_t * a)
+{
+    return vld1q_s64_x3 (a);
+}
+
+float32x4x3_t test_vld1q_f32_x3 (float32_t * a)
+{
+    return vld1q_f32_x3 (a);
+}
+
+poly8x16x3_t test_vld1q_p8_x3 (poly8_t * a)
+{
+    return vld1q_p8_x3 (a);
+}
+
+poly16x8x3_t test_vld1q_p16_x3 (poly16_t * a)
+{
+    return vld1q_p16_x3 (a);
+}
+
 /* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
+
 /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
+
 /* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } }  */
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
+/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } }  */
 
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
index 5f6fc98..4138fe9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_bf16_xN_1.c
@@ -10,4 +10,10 @@ bfloat16x8x2_t test_vld1q_bf16_x2 (bfloat16_t * a)
     return vld1q_bf16_x2 (a);
 }
 
+bfloat16x8x3_t test_vld1q_bf16_x3 (bfloat16_t * a)
+{
+    return vld1q_bf16_x3 (a);
+}
+
 /* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
index aecf491..01640d7 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_fp16_xN_1.c
@@ -10,5 +10,10 @@ float16x8x2_t test_vld1q_f16_x2 (float16_t * a)
     return vld1q_f16_x2 (a);
 }
 
-/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
+float16x8x3_t test_vld1q_f16_x3 (float16_t * a)
+{
+    return vld1q_f16_x3 (a);
+}
 
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } }  */
+/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } }  */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
index 04ceb5e..ae2ab36 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vld1q_p64_xN_1.c
@@ -10,5 +10,10 @@ poly64x2x2_t test_vld1q_p64_x2 (poly64_t * a)
     return vld1q_p64_x2 (a);
 }
 
-/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */
+poly64x2x3_t test_vld1q_p64_x3 (poly64_t * a)
+{
+    return vld1q_p64_x3 (a);
+}
 
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } }  */
+/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } }  */