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authorPan Li <pan2.li@intel.com>2025-07-25 22:11:13 +0800
committerPan Li <pan2.li@intel.com>2025-07-27 11:12:34 +0800
commit62f8a246bbaa1a1f5aedba4c84f7fe4c7eca799f (patch)
treeb6458e4bf3baeac246e3d55a88bdbb21677672c6 /gcc/testsuite/rust/compile/macros/mbe/macro-issue2653.rs
parentfb9e54393dc12f3d87abad454651262061736e9c (diff)
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RISC-V: Fix another vf FP16 combine run test failuresHEADtrunkmaster
Like Robin's fix for vf combine f16.c run tests, there is still another failures similar. This patch would like to fix it as previous. will commit it directly if the CI agrees. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: Add zvfh requirements and options. * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
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