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authorPan Li <pan2.li@intel.com>2025-07-31 12:32:24 +0800
committerPan Li <pan2.li@intel.com>2025-08-05 09:37:10 +0800
commit01a784e7c5e724be3ff5ab663eb288d3ed66100b (patch)
treeeb31c0175efc46a77608fb6377be31d4d8c400ca /gcc/testsuite/objc
parentaa558046c09889df871a5198132d5237e939d64a (diff)
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RISC-V: Fix scalar code-gen of unsigned SAT_MULHEADtrunkmaster
The previous code-gen of scalar unsigned SAT_MUL, aka usmul. Leverage the mulhs by mistake, it should be mulhu for the hight bit result of mul. Thus, this patch would like to make it correct. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_xmode_usmul): Take umulhu for high bits mul result. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c: Add mulhu asm check. * gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
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