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authorJeff Law <jlaw@ventanamicro.com>2025-08-12 20:29:50 -0600
committerJeff Law <jlaw@ventanamicro.com>2025-08-12 20:31:34 -0600
commit2e2589616ac18a0473e4f1e05dec6903d8131740 (patch)
tree0d93dea1280a7cbcc8d1700913d8af6450e5f824 /gcc/testsuite/gm2/pimlib/run/pass/testnan.mod
parent67e0490922691305699fb17922e44bce304e0505 (diff)
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[RISC-V][PR target/121113] Handle HFmode in various insn reservationsHEADtrunkmaster
So this is a minor bug in a few DFA descriptions such as the Xiangshan and a couple of the SiFive descriptions. While Xiangshan covers every insn type, some of the reservations check the mode of the operation. Concretely the fdiv/fsqrt unit reservations vary based on the mode. They handled DF/SF, but not HF (the relevant iterators don't include BF). This patch just adds HF support with the same characteristics as SF. Those who know these designs better could perhaps improve the reservation, but this at least keeps us from aborting. I did check the other published DFAs for mode dependent reservations. That's show I found the p400/p600 issue. Tested in my tester, waiting for CI to render its verdict before pushing. PR target/121113 gcc/ * config/riscv/sifive-p400.md: Handle HFmode for fdiv/fsqrt. * config/riscv/sifive-p600.md: Likewise. * config/riscv/xiangshan.md: Likewise. gcc/testsuite/ * gcc.target/riscv/pr121113.c: New test.
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