RISC-V: Introduce gcc attribute riscv_rvv_vector_bits for RVV

This patch would like to introduce one new gcc attribute for RVV.
This attribute is used to define fixed-length variants of one
existing sizeless RVV types.

This attribute is valid if and only if the mrvv-vector-bits=zvl, the only
one args should be the integer constant and its' value is terminated
by the LMUL and the vector register bits in zvl*b.  For example:

typedef vint32m2_t fixed_vint32m2_t __attribute__((riscv_rvv_vector_bits(128)));

The above type define is valid when -march=rv64gc_zve64d_zvl64b
(aka 2(m2) * 64 = 128 for vin32m2_t), and will report error when
-march=rv64gcv_zvl128b similar to below.

"error: invalid RVV vector size '128', expected size is '256' based on
LMUL of type and '-mrvv-vector-bits=zvl'"

Meanwhile, a pre-define macro __riscv_v_fixed_vlen is introduced to
represent the fixed vlen in a RVV vector register.

For the vint*m*_t below operations are allowed.
* The sizeof.
* The global variable(s).
* The element of union and struct.
* The cast to other equalities.
* CMP: >, <, ==, !=, <=, >=
* ALU: +, -, *, /, %, &, |, ^, >>, <<, ~, -

The CMP will return vint*m*_t the same as aarch64 sve. For example:
typedef vint32m1_t fixed_vint32m1_t __attribute__((riscv_rvv_vector_bits(128)));
fixed_vint32m1_t less_than (fixed_vint32m1_t a, fixed_vint32m1_t b)
{
  return a < b;
}

For the vfloat*m*_t below operations are allowed.
* The sizeof.
* The global variable(s).
* The element of union and struct.
* The cast to other equalities.
* CMP: >, <, ==, !=, <=, >=
* ALU: +, -, *, /, -

The CMP will return vfloat*m*_t the same as aarch64 sve. For example:
typedef vfloat32m1_t fixed_vfloat32m1_t __attribute__((riscv_rvv_vector_bits(128)));
fixed_vfloat32m1_t less_than (fixed_vfloat32m1_t a, fixed_vfloat32m1_t b)
{
  return a < b;
}

For the vbool*_t types only below operations are allowed except
the CMP and ALU. The CMP and ALU operations on vbool*_t is not
well defined currently.
* The sizeof.
* The global variable(s).
* The element of union and struct.
* The cast to other equalities.

For the vint*x*m*_t tuple types are not suppored in this patch which is
compatible with clang.

This patch passed the below testsuites.
* The riscv fully regression tests.

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
	macro __riscv_v_fixed_vlen when zvl.
	* config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
	New static func to take care of the RVV types decorated by
	the attributes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-1.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-10.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-11.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-12.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-13.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-14.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-15.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-16.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-17.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-18.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-2.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-3.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-4.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-5.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-6.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-7.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-8.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits-9.c: New test.
	* gcc.target/riscv/rvv/base/riscv_rvv_vector_bits.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

0 files changed, 0 insertions, 0 deletions