Improve initial code generation for addsi/adddiHEADtrunkmaster

This is a patch primarily from Shreya, though I think she cribbed some
code from Philipp that we had internally within Ventana and I made some
minor adjustments as well.

So the basic idea here is similar to her work on logical ops --
specifically when we can generate more efficient code at expansion time,
then do so.  In some cases the net is better code; in other cases we
lessen reliance on mvconst_internal and finally it provides
infrastructure that I think will help address an issue Paul Antoine
reported a little while back.

The most obvious case is using paired addis from initial code generation
for some constants.  It will also use a shNadd insn when the cost to
synthesize the original value is higher than the right-shifted value.
Finally it will negate the constant and use "sub"  if the negated
constant is cheaper than the original constant.

There's more work to do in here, particularly WRT 32 bit objects for
rv64.  Shreya is looking at that right now.  There may also be cases
where another shNadd or addi would be profitable.  We haven't really
explored those cases in any detail, while there may be cases to handle,
it's unclear how often they occur in practice.

I don't want to remove the define_insn_and_split for the paired addi
cases yet.  I think that likely happens as a side effect of fixing Paul
Antoine's issue.

Bootstrapped and regression tested on a BPI & Pioneer box.  Will
obviously wait for the pre-commit tester before moving forward.

Jeff
PR target/120603
gcc/
	* config/riscv/riscv-protos.h (synthesize_add): Add prototype.
	* config/riscv/riscv.cc (synthesize_add): New function.
	* config/riscv/riscv.md (addsi3): Allow any constant as operands[2]
	in the expander.  Force the constant into a register as needed for
	TARGET_64BIT.  Use synthesize_add for !TARGET_64BIT.
	(*adddi3): Renamed from adddi3.
	(adddi3): New expander.  Use synthesize_add.

gcc/testsuite
	* gcc.target/riscv/add-synthesis-1.c: New test.

Co-authored-by: Jeff Law  <jlaw@ventanamicro.com>
Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

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