constraints.md (we constraint): New constraint for 64-bit power9 vector support.

[gcc]
2015-11-13  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/constraints.md (we constraint): New constraint for
	64-bit power9 vector support.
	(wL constraint): New constraint for the element in a vector that
	can be addressed by the MFVSRLD instruction.

	* config/rs6000/rs6000-protos.h (convert_float128_to_int): Add
	declaration.
	(convert_int_to_float128): Likewise.
	(rs6000_generate_compare): Add support for ISA 3.0 (power9)
	hardware support for IEEE 128-bit floating point.
	(rs6000_expand_float128_convert): Likewise.
	(convert_float128_to_int): Likewise.
	(convert_int_to_float128): Likewise.

	* config/rs6000/rs6000.md (UNSPEC_ROUND_TO_ODD): New unspecs for
	ISA 3.0 hardware IEEE 128-bit floating point.
	(UNSPEC_IEEE128_MOVE): Likewise.
	(UNSPEC_IEEE128_CONVERT): Likewise.
	(FMA_F): Add support for IEEE 128-bit floating point hardware
	support.
	(Ff): Add support for DImode.
	(Fv): Likewise.
	(any_fix code iterator): New and updated iterators for IEEE
	128-bit floating point hardware support.
	(any_float code iterator): Likewise.
	(s code attribute): Likewise.
	(su code attribute): Likewise.
	(az code attribute): Likewise.
	(uns code attribute): Likewise.
	(neg<mode>2, FLOAT128 iterator): Add support for IEEE 128-bit
	floating point hardware support.
	(abs<mode>2, FLOAT128 iterator): Likewise.
	(add<mode>3, IEEE128 iterator): New insns for IEEE 128-bit
	floating point hardware.
	(sub<mode>3, IEEE128 iterator): Likewise.
	(mul<mode>3, IEEE128 iterator): Likewise.
	(div<mode>3, IEEE128 iterator): Likewise.
	(copysign<mode>3, IEEE128 iterator): Likewise.
	(sqrt<mode>2, IEEE128 iterator): Likewise.
	(neg<mode>2, IEEE128 iterator): Likewise.
	(abs<mode>2, IEEE128 iterator): Likewise.
	(nabs<mode>2, IEEE128 iterator): Likewise.
	(fma<mode>4_hw, IEEE128 iterator): Likewise.
	(fms<mode>4_hw, IEEE128 iterator): Likewise.
	(nfma<mode>4_hw, IEEE128 iterator): Likewise.
	(nfms<mode>4_hw, IEEE128 iterator): Likewise.
	(extend<SFDF:mode><IEEE128:mode>2_hw): Likewise.
	(trunc<mode>df2_hw, IEEE128 iterator): Likewise.
	(trunc<mode>sf2_hw, IEEE128 iterator): Likewise.
	(fix_fixuns code attribute): Likewise.
	(float_floatuns code attribute): Likewise.
	(fix<uns>_<mode>si2_hw): Likewise.
	(fix<uns>_<mode>di2_hw): Likewise.
	(float<uns>_<mode>si2_hw): Likewise.
	(float<uns>_<mode>di2_hw): Likewise.
	(xscvqp<su>wz_<mode>): Likewise.
	(xscvqp<su>dz_<mode>): Likewise.
	(xscv<su>dqp_<mode): Likewise.
	(ieee128_mfvsrd): Likewise.
	(ieee128_mfvsrwz): Likewise.
	(ieee128_mtvsrw): Likewise.
	(ieee128_mtvsrd): Likewise.
	(trunc<mode>df2_odd): Likewise.
	(cmp<mode>_h): Likewise.
	(128-bit GPR splitters): Don't split a 128-bit move that is a
	direct move between GPR and vector registers using ISA 3.0 direct
	move instructions.
	(<u>mul<mode><dmode>3): Add support for the ISA 3.0 integer
	multiply-add instruction.

	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add ISA 3.0
	debugging.
	(rs6000_init_hard_regno_mode_ok): If ISA 3.0 and 64-bit, enable we
	constraint.  Disable the VSX<->GPR direct move helpers if we have
	the MFVSRLD and MTVSRDD instructions.
	(rs6000_secondary_reload_simple_move): Add support for doing
	vector direct moves directly without additional scratch registers
	if we have ISA 3.0 instructions.
	(rs6000_secondary_reload_direct_move): Update comments.
	(rs6000_output_move_128bit): Add support for ISA 3.0 vector
	instructions.

	* config/rs6000/vsx.md (vsx_mov<mode>): Add support for ISA 3.0
	direct move instructions.
	(vsx_movti_64bit): Likewise.
	(vsx_extract_<mode>): Likewise.

	* config/rs6000/rs6000.h (VECTOR_ELEMENT_MFVSRLD_64BIT): New
	macros for ISA 3.0 direct move instructions.
	(TARGET_DIRECT_MOVE_128): Likewise.
	(TARGET_MADDLD): Add support for the ISA 3.0 integer multiply-add
	instruction.

	* doc/md.texi (RS/6000 constraints): Document we, wF, wG, wL
	constraints.  Update wa documentation to say not to use %x<n> on
	instructions that only take Altivec registers.

[gcc/testsuite]
2015-11-13  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/float128-hw.c: New test for IEEE 128-bit
	hardware floating point support.

	* gcc.target/powerpc/direct-move-vector.c: New test for 128-bit
	vector direct move instructions.

	* gcc.target/powerpc/maddld.c: New test.

From-SVN: r230342

3 files changed, 71 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c b/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c
new file mode 100644
index 0000000..1e8504e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/direct-move-vector.c
@@ -0,0 +1,33 @@
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+/* Check code generation for direct move for long types.  */
+
+void
+test (vector double *p)
+{
+  vector double v1 = *p;
+  vector double v2;
+  vector double v3;
+  vector double v4;
+
+  /* Force memory -> FPR load.  */
+  __asm__ (" # reg %x0" : "+d" (v1));
+
+  /* force VSX -> GPR direct move.  */
+  v2 = v1;
+  __asm__ (" # reg %0" : "+r" (v2));
+
+  /* Force GPR -> Altivec direct move.  */
+  v3 = v2;
+  __asm__ (" # reg %x0" : "+v" (v3));
+  *p = v3;
+}
+
+/* { dg-final { scan-assembler "mfvsrd"  } } */
+/* { dg-final { scan-assembler "mfvsrld" } } */
+/* { dg-final { scan-assembler "mtvsrdd" } } */
+
+
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-hw.c b/gcc/testsuite/gcc.target/powerpc/float128-hw.c
new file mode 100644
index 0000000..71a0c24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/float128-hw.c
@@ -0,0 +1,18 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-require-effective-target powerpc_float128_hw_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+__float128 f128_add (__float128 a, __float128 b) { return a+b; }
+__float128 f128_sub (__float128 a, __float128 b) { return a-b; }
+__float128 f128_mul (__float128 a, __float128 b) { return a*b; }
+__float128 f128_div (__float128 a, __float128 b) { return a/b; }
+__float128 f128_fma (__float128 a, __float128 b, __float128 c) { return (a*b)+c; }
+long f128_cmove (__float128 a, __float128 b, long c, long d) { return (a == b) ? c : d; }
+
+/* { dg-final { scan-assembler "xsaddqp"  } } */
+/* { dg-final { scan-assembler "xssubqp"  } } */
+/* { dg-final { scan-assembler "xsmulqp"  } } */
+/* { dg-final { scan-assembler "xsdivqp"  } } */
+/* { dg-final { scan-assembler "xsmaddqp" } } */
+/* { dg-final { scan-assembler "xscmpuqp" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/maddld.c b/gcc/testsuite/gcc.target/powerpc/maddld.c
new file mode 100644
index 0000000..c2b0c17
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/maddld.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p9modulo_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+long
+s_madd (long a, long b, long c)
+{
+  return (a * b) + c;
+}
+
+unsigned long
+u_madd (unsigned long a, unsigned long b, unsigned long c)
+{
+  return (a * b) + c;
+}
+
+/* { dg-final { scan-assembler-times "maddld " 2 } } */
+/* { dg-final { scan-assembler-not   "mulld "    } } */
+/* { dg-final { scan-assembler-not   "add "      } } */