RISC-V: Fix incorrect VXRM configuration in mode switching for CALL and ASM

Currently mode switching incorrect codegen for the following case:
void fn (void);

void f (void * in, void *out, int32_t x, int n, int m)
{
  for (int i = 0; i < n; i++) {
    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
    fn ();
    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
    __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
  }
}

Before this patch:

Preheader:
  ...
  csrwi vxrm,2
Loop Body:
  ... (no cswri vxrm,2)
  vaadd.vx
  ...
  vaadd.vx
  ...

This codegen is incorrect.

After this patch:

Preheader:
  ...
  csrwi vxrm,2
Loop Body:
  ...
  vaadd.vx
  ...
  csrwi vxrm,2
  ...
  vaadd.vx
  ...

cross-compile build PASS and regression PASS.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>

gcc/ChangeLog:

	* config/riscv/riscv.cc (global_state_unknown_p): New function.
	(riscv_mode_after): Fix incorrect VXM.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/vxrm-11.c: New test.
	* gcc.target/riscv/rvv/base/vxrm-12.c: New test.

2 files changed, 38 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
new file mode 100644
index 0000000..7f637a8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-11.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void fn (void);
+
+void f (void * in, void *out, int32_t x, int n, int m)
+{
+  for (int i = 0; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    fn ();
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
new file mode 100644
index 0000000..c3ab509
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vxrm-12.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f (void * in, void *out, int32_t x, int n, int m)
+{
+  for (int i = 0; i < n; i++) {
+    vint32m1_t v = __riscv_vle32_v_i32m1 (in + i, 4);
+    vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in + 100 + i, 4);
+    vint32m1_t v3 = __riscv_vaadd_vx_i32m1 (v2, 0, VXRM_RDN, 4);
+    asm volatile ("csrwi\tvxrm,1");
+    v3 = __riscv_vaadd_vx_i32m1 (v3, 3, VXRM_RDN, 4);
+    __riscv_vse32_v_i32m1 (out + 100 + i, v3, 4);
+  }
+}
+
+/* { dg-final { scan-assembler-times {csrwi\s+vxrm,\s*2} 2 } } */