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authorEric Botcazou <ebotcazou@adacore.com>2016-10-21 09:16:29 +0000
committerEric Botcazou <ebotcazou@gcc.gnu.org>2016-10-21 09:16:29 +0000
commit8572922996bd2db0400ccbf5043b1fdbff2fd936 (patch)
tree1c3213226bdaf9d03e4c453e15e1c9b5701c2a83 /gcc/testsuite/gcc.target/sparc/overflow-3.c
parentd17f2c3b496cce8c1eea2dab929c28e5899f9cc4 (diff)
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sparc-modes.def (CCV): New.
* config/sparc/sparc-modes.def (CCV): New. (CCXV): Likewise. * config/sparc/predicates.md (v_comparison_operator): New. (icc_comparison_operator): Add support for CCV/CCXV. (xcc_comparison_operator): Likewise. * config/sparc/sparc.c (output_cbranch): Likewise. (sparc_print_operand): Likewise. * config/sparc/sparc.md (UNSPEC_{ADD,SUB,NEG}V): New constants. (uaddvdi4): New expander. (addvdi4): Likewise. (uaddvdi4_sp32): New instruction. (addvdi4_sp32): Likewise. (uaddvsi4): New expander. (addvsi4): Likewise. (cmp_ccc_plus_sltu_set): New instruction. (cmp_ccv_plus): Likewise. (cmp_ccxv_plus): Likewise. (cmp_ccv_plus_set): Likewise. (cmp_ccxv_plus_set): Likewise. (cmp_ccv_plus_sltu_set): Likewise. (uaddvdi4): New expander. (subvdi4): Likewise. (usubdi4_sp32): New instruction. (subvdi4_sp32): Likewise. (usubvsi4): New expander. (subvsi4): Likewise. (cmpsi_minus_sltu_set): New instruction. (cmp_ccv_minus): Likewise. (cmp_ccxv_minus): Likewise. (cmp_ccv_minus_set): Likewise. (cmp_ccxv_minus_set): Likewise. (cmp_ccv_minus_sltu_set): Likewise. (unegvdi3): New expander. (negvdi3): Likewise. (unegdi3_sp32): New instruction. (negvdi3_sp32): Likewise. (unegvsi3): New expander. (negvsi3): Likewise. (cmp_ccc_neg_sltu_set): New instruction. (cmp_ccv_neg): Likewise. (cmp_ccxv_neg): Likewise. (cmp_ccv_neg_set): Likewise. (cmp_ccxv_neg_set): Likewise. (cmp_ccv_neg_sltu_set): Likewise. From-SVN: r241397
Diffstat (limited to 'gcc/testsuite/gcc.target/sparc/overflow-3.c')
-rw-r--r--gcc/testsuite/gcc.target/sparc/overflow-3.c44
1 files changed, 44 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
new file mode 100644
index 0000000..31b3264
--- /dev/null
+++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+/* { dg-require-effective-target lp64 } */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+bool my_uadd_overflow (uint64_t a, uint64_t b, uint64_t *res)
+{
+ return __builtin_add_overflow (a, b, res);
+}
+
+bool my_usub_overflow (uint64_t a, uint64_t b, uint64_t *res)
+{
+ return __builtin_sub_overflow (a, b, res);
+}
+
+bool my_uneg_overflow (uint64_t a, uint64_t *res)
+{
+ return __builtin_sub_overflow (0, a, res);
+}
+
+bool my_add_overflow (int64_t a, int64_t b, int64_t *res)
+{
+ return __builtin_add_overflow (a, b, res);
+}
+
+bool my_sub_overflow (int64_t a, int64_t b, int64_t *res)
+{
+ return __builtin_sub_overflow (a, b, res);
+}
+
+bool my_neg_overflow (int64_t a, int64_t *res)
+{
+ return __builtin_sub_overflow (0, a, res);
+}
+
+/* { dg-final { scan-assembler-times "addcc\t%" 2 } } */
+/* { dg-final { scan-assembler-times "subcc\t%" 4 } } */
+/* { dg-final { scan-assembler-times "movlu\t%" 1 } } */
+/* { dg-final { scan-assembler-times "blu" 2 } } */
+/* { dg-final { scan-assembler-times "bvs" 3 } } */
+/* { dg-final { scan-assembler-not "cmp\t%" } } */
+/* { dg-final { scan-assembler-not "save\t%" } } */