diff options
| author | Kuan-Lin Chen <rufus@andestech.com> | 2025-09-03 17:03:05 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2025-09-03 17:03:05 -0600 |
| commit | 2963f5f7bd6db0e3f023fadb4c9c3d9e1a3fdcad (patch) | |
| tree | 5060932523c3fb96c1f83ad8a52081e6469cd623 /gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c | |
| parent | e1fb7db6954d08860119f6b34db0c7d2490681de (diff) | |
| download | gcc-master.zip gcc-master.tar.gz gcc-master.tar.bz2 | |
This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.
gcc/ChangeLog:
* config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
* config/riscv/riscv.md (truncsfbf2): Add TARGET_XANDESBFHCVT support.
(extendbfsf2): Ditto.
* config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
* config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xandes/xandesbfhcvt-1.c: New test.
* gcc.target/riscv/xandes/xandesbfhcvt-2.c: New test.
Diffstat (limited to 'gcc/testsuite/gcc.target/powerpc/sse2-ucomisd-4.c')
0 files changed, 0 insertions, 0 deletions