pr36493.c: Call check_vect.

	* gcc.dg/vect/pr36493.c: Call check_vect.
	* gcc.dg/vect/pr37539.c: Likewise.
	* gcc.dg/vect/vect-nest-cycle-3.c: Call check_vect earlier.
	* tree-vect.h (check_vect): Use cpuid for x86.

From-SVN: r154666

4 files changed, 35 insertions, 6 deletions

diff --git a/gcc/testsuite/gcc.dg/vect/pr36493.c b/gcc/testsuite/gcc.dg/vect/pr36493.c
index 0a330b0..98517df 100644
--- a/gcc/testsuite/gcc.dg/vect/pr36493.c
+++ b/gcc/testsuite/gcc.dg/vect/pr36493.c
@@ -8,6 +8,8 @@ main (void)
   int i;
   long x[12] __attribute__((aligned(__BIGGEST_ALIGNMENT__)));
 
+  check_vect ();
+
   x[0] = 1;
   for (i = 0; i < 12; i++)
     x[i] = i;
diff --git a/gcc/testsuite/gcc.dg/vect/pr37539.c b/gcc/testsuite/gcc.dg/vect/pr37539.c
index 1d569a9..1e73425 100644
--- a/gcc/testsuite/gcc.dg/vect/pr37539.c
+++ b/gcc/testsuite/gcc.dg/vect/pr37539.c
@@ -30,6 +30,8 @@ int main ()
 {
   int d[256], src[128], i;
  
+  check_vect ();
+
   for (i = 0; i < 128; i++)
     src[i] = i; 
   
diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h
index e080a6d..2f21c2b 100644
--- a/gcc/testsuite/gcc.dg/vect/tree-vect.h
+++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h
@@ -1,16 +1,21 @@
 /* Check if system supports SIMD */
 #include <signal.h>
 
+#if defined(__i386__) || defined(__x86_64__)
+# include "cpuid.h"
+#endif
+
 extern void abort (void);
 extern void exit (int);
 
-void
+static void
 sig_ill_handler (int sig)
 {
   exit(0);
 }
 
-void check_vect (void)
+static void __attribute__((noinline))
+check_vect (void)
 {
   signal(SIGILL, sig_ill_handler);
 #if defined(__PAIRED__)
@@ -20,8 +25,28 @@ void check_vect (void)
   /* Altivec instruction, 'vor %v0,%v0,%v0'.  */
   asm volatile (".long 0x10000484");
 #elif defined(__i386__) || defined(__x86_64__)
-  /* SSE2 instruction: movsd %xmm0,%xmm0 */
-  asm volatile (".byte 0xf2,0x0f,0x10,0xc0");
+  {
+    int a, b, c, d, want_level, want_c, want_d;
+
+    /* Determine what instruction set we've been compiled for, and detect
+       that we're running with it.  This allows us to at least do a compile
+       check for, e.g. SSE4.1 when the machine only supports SSE2.  */
+# ifdef __XOP__
+    want_level = 0x80000001, want_c = bit_XOP, want_d = 0;
+# elif defined(__AVX__)
+    want_level = 1, want_c = bit_AVX, want_d = 0;
+# elif defined(__SSE4_1__)
+    want_level = 1, want_c = bit_SSE4_1, want_d = 0;
+# elif defined(__SSSE3__)
+    want_level = 1, want_c = bit_SSSE3, want_d = 0;
+# else
+    want_level = 1, want_c = 0, want_d = bit_SSE2;
+# endif
+
+    if (!__get_cpuid (want_level, &a, &b, &c, &d)
+	|| ((c & want_c) | (d & want_d)) == 0)
+      exit (0);
+  }
 #elif defined(__sparc__)
   asm volatile (".word\t0x81b007c0");
 #elif defined(__arm__)
diff --git a/gcc/testsuite/gcc.dg/vect/vect-nest-cycle-3.c b/gcc/testsuite/gcc.dg/vect/vect-nest-cycle-3.c
index 70fa6b8..112f146 100644
--- a/gcc/testsuite/gcc.dg/vect/vect-nest-cycle-3.c
+++ b/gcc/testsuite/gcc.dg/vect/vect-nest-cycle-3.c
@@ -39,6 +39,8 @@ int main (void)
 { 
   int i, j;
 
+  check_vect ();
+  
   for (i = 0; i < N; i++)
     for (j = 0; j < N; j++)
       {
@@ -46,8 +48,6 @@ int main (void)
         c[i][j] = i+j;
       }
          
-  check_vect ();
-  
   main1 ();
 
   return 0;