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authorPan Li <pan2.li@intel.com>2025-08-24 16:36:00 +0800
committerPan Li <pan2.li@intel.com>2025-08-31 09:41:25 +0800
commitaf979624128b24303c2e29b3f2535445877056ec (patch)
treecb01ab47278b408c700954a60d7a7df1afdc487b /gcc/testsuite/g++.dg/pr90773-1c.C
parentf4851381678127881461ef56f210d92cbc4c978e (diff)
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RISC-V: Add test case for unsigned scalar SAT_MUL form 4HEADtrunkmaster
The form 4 of unsigned scalar SAT_MUL is covered in middle-expand alreay, add test case here to cover form 4. The below test suites are passed for this patch series. * The rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat/sat_arith.h: Add test helper macros. * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv32.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u16-from-u64.rv64.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv32.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u32-from-u64.rv64.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u64-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u16.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv32.c: New test. * gcc.target/riscv/sat/sat_u_mul-5-u8-from-u64.rv64.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u16-from-u64.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u32-from-u64.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u64-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u128.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u16.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u32.c: New test. * gcc.target/riscv/sat/sat_u_mul-run-5-u8-from-u64.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/testsuite/g++.dg/pr90773-1c.C')
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