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authorRobin Dapp <rdapp@ventanamicro.com>2025-03-11 14:30:48 +0100
committerRobin Dapp <rdapp@ventanamicro.com>2025-03-17 09:51:59 +0100
commitb58a0af4e2e28b395a3cb4b7283f16f05c0cf3c8 (patch)
tree30fc458e5a8541d67b42caa12766cc9c45adb497 /gcc/rust/util
parentf4f7216c56fe2f67c72db5b7c4afa220725f3ed1 (diff)
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RISC-V: Mask values before initializing bitmask vector [PR119114].
In the somewhat convoluted vector code of PR119114 we extract a <signed-boolean:1> mask value from a vector mask. After some middle-end simplifications we end up with a value of -2. Its lowest bit is correctly unset representing "false". When initializing a bitmak vector from values we compare the full value/register against zero instead of just the last bit. This causes erroneous mask values. This patch masks the values by & 0x1 before comparing against 0. PR target/119114 gcc/ChangeLog: * config/riscv/autovec.md: Apply & 0x1 mask when initializing bitmask vector. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr119114.c: New test.
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