RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax

ICE:
bug.c:10:1: error: unrecognizable insn:
   10 | }
      | ^
(insn 10 9 11 2 (set (reg:V4SI 140)
        (unspec:V4SI [
                (unspec:V4BI [
                        (const_vector:V4BI [
                                (const_int 1 [0x1]) repeated x4
                            ])
                        (const_int 4 [0x4])
                        (const_int 2 [0x2]) repeated x3
                        (reg:SI 66 vl)
                        (reg:SI 67 vtype)
                    ] UNSPEC_VPREDICATE)
                (unspec:V4SI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF)
                (subreg:V4SI (reg:V2DI 138 [ v ]) 0)
                (subreg:SI (reg/v:DI 136 [ b ]) 0)
            ] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1
     (nil))

The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI which is totally same as V4SI
on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax.

The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use get_vector_mode to get
right mode.

	PR target/112597

gcc/ChangeLog:

	* config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
	* config/riscv/vector.md: Fix slide1 intermediate mode bug.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.

0 files changed, 0 insertions, 0 deletions