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| author | Andrew Stubbs <ams@codesourcery.com> | 2020-09-10 10:10:32 +0100 |
|---|---|---|
| committer | Andrew Stubbs <ams@codesourcery.com> | 2020-09-11 10:55:32 +0100 |
| commit | 8ae0de5621120b16295fe6b73ca044d4c576af6d (patch) | |
| tree | bc0346e655274ab0cf77e17d375e9766aa67d1d7 /gcc/loop-init.c | |
| parent | 054fc495fac5478a119715d10e1dd76442851bb5 (diff) | |
| download | gcc-8ae0de5621120b16295fe6b73ca044d4c576af6d.zip gcc-8ae0de5621120b16295fe6b73ca044d4c576af6d.tar.gz gcc-8ae0de5621120b16295fe6b73ca044d4c576af6d.tar.bz2 | |
amdgcn: align TImode registers
This prevents execution failures caused by partially overlapping input and
output registers. This is the same solution already used for DImode.
gcc/ChangeLog:
* config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align TImode registers.
* config/gcn/gcn.md: Assert that TImode registers do not early clobber.
Diffstat (limited to 'gcc/loop-init.c')
0 files changed, 0 insertions, 0 deletions