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| author | Richard Sandiford <richard.sandiford@arm.com> | 2024-10-07 13:03:02 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2024-10-07 13:03:02 +0100 |
| commit | 1048ebbbdc98a5928a974356d7f4244603b6bd32 (patch) | |
| tree | f9ff1d6e6af658a8b27a7583a0467a35695f3635 /gcc/gcov.cc | |
| parent | fce02baff53bbcb673f41ea18668103edb2f7c00 (diff) | |
| download | gcc-1048ebbbdc98a5928a974356d7f4244603b6bd32.zip gcc-1048ebbbdc98a5928a974356d7f4244603b6bd32.tar.gz gcc-1048ebbbdc98a5928a974356d7f4244603b6bd32.tar.bz2 | |
aarch64: Handle SVE modes in aarch64_evpc_reencode [PR116583]
For Advanced SIMD modes, aarch64_evpc_reencode tests whether
a permute in a narrow element mode can be done more cheaply
in a wider mode. For example, { 0, 1, 8, 9, 4, 5, 12, 13 }
on V8HI is a natural TRN1 on V4SI ({ 0, 4, 2, 6 }).
This patch extends the code to handle SVE data and predicate
modes as well. This is a prerequisite to getting good results
for PR116583.
gcc/
PR target/116583
* config/aarch64/aarch64.cc (aarch64_coalesce_units): New function,
extending the Advanced SIMD handling from...
(aarch64_evpc_reencode): ...here to SVE data and predicate modes.
gcc/testsuite/
PR target/116583
* gcc.target/aarch64/sve/permute_1.c: New test.
* gcc.target/aarch64/sve/permute_2.c: Likewise.
* gcc.target/aarch64/sve/permute_3.c: Likewise.
* gcc.target/aarch64/sve/permute_4.c: Likewise.
Diffstat (limited to 'gcc/gcov.cc')
0 files changed, 0 insertions, 0 deletions