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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:25 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:25 +0000 |
| commit | a17ab4b6add6a7b7cedbef39af442ca99f7cb3f8 (patch) | |
| tree | 7e53d2b4d7249f08dff03f36144e15ce8759b950 /gcc/gcov.c | |
| parent | da076a8b12c17b10cfe2e6a9c5ea84aa0a0f5ebf (diff) | |
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VAX: Provide the `ctz' operation
Our `ffssi2_internal' pattern and the machine FFS instruction, which
technically is a bit-field operation, match the `ctz' operation exactly,
with the result produced for the bit-field source operand of zero equal
to its width as specified with another machine instruction operand, not
directly expressed in RTL and currently hardcoded in the assembly code
produced. In our terms this is the bit size of the machine mode used,
and although it's SImode now let's be flexible for an upcoming change.
The operation also sets the Z condition code according to the value of
the source operand.
gcc/
* config/vax/builtins.md (ffssi2_internal): Rename insn to...
(ctzsi2): ... this. Update the RTL operation.
(ffssi2): Update accordingly.
* config/vax/vax.c (vax_notice_update_cc): Handle CTZ.
* config/vax/vax.h (CTZ_DEFINED_VALUE_AT_ZERO): New macro.
gcc/testsuite/
* gcc.target/vax/ctzsi.c: New test.
Diffstat (limited to 'gcc/gcov.c')
0 files changed, 0 insertions, 0 deletions