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| author | Jennifer Schmitz <jschmitz@nvidia.com> | 2024-10-17 02:31:47 -0700 |
|---|---|---|
| committer | Jennifer Schmitz <jschmitz@nvidia.com> | 2024-10-24 11:54:27 +0200 |
| commit | f6fbc0d2422ce9bea6a23226f4a13a76ffd1784b (patch) | |
| tree | 024aec1f3e54777a5ece46017dcf9f8bd6d2e30c /gcc/gcc-urlifier.cc | |
| parent | 3e7549ece7c6b90b9e961778361ee2b65bf104a9 (diff) | |
| download | gcc-f6fbc0d2422ce9bea6a23226f4a13a76ffd1784b.zip gcc-f6fbc0d2422ce9bea6a23226f4a13a76ffd1784b.tar.gz gcc-f6fbc0d2422ce9bea6a23226f4a13a76ffd1784b.tar.bz2 | |
SVE intrinsics: Fold svsra with op1 all zeros to svlsr/svasr.
A common idiom in intrinsics loops is to have accumulator intrinsics
in an unrolled loop with an accumulator initialized to zero at the beginning.
Propagating the initial zero accumulator into the first iteration
of the loop and simplifying the first accumulate instruction is a
desirable transformation that we should teach GCC.
Therefore, this patch folds svsra to svlsr/svasr if op1 is all zeros,
producing the lower latency instructions LSR/ASR instead of USRA/SSRA.
We implemented this optimization in svsra_impl::fold.
Tests were added to check the produced assembly for use of LSR/ASR.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-by: Jennifer Schmitz <jschmitz@nvidia.com>
gcc/
* config/aarch64/aarch64-sve-builtins-sve2.cc
(svsra_impl::fold): Fold svsra to svlsr/svasr if op1 is all zeros.
gcc/testsuite/
* gcc.target/aarch64/sve2/acle/asm/sra_s32.c: New test.
* gcc.target/aarch64/sve2/acle/asm/sra_s64.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/sra_u32.c: Likewise.
* gcc.target/aarch64/sve2/acle/asm/sra_u64.c: Likewise.
Diffstat (limited to 'gcc/gcc-urlifier.cc')
0 files changed, 0 insertions, 0 deletions