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| author | Pan Li <pan2.li@intel.com> | 2024-09-23 13:43:50 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-10-24 09:46:52 +0800 |
| commit | 03b469ee4768118807a3c74891c3c426b0c145ef (patch) | |
| tree | 6e2c26e42adb5f36ce2217424c7e9dc2b4031328 /gcc/gcc-urlifier.cc | |
| parent | fa546b6641e34d55f8a498bd863fd9e6d06e991e (diff) | |
| download | gcc-03b469ee4768118807a3c74891c3c426b0c145ef.zip gcc-03b469ee4768118807a3c74891c3c426b0c145ef.tar.gz gcc-03b469ee4768118807a3c74891c3c426b0c145ef.tar.bz2 | |
RISC-V: Add testcases for form 4 of signed vector SAT_ADD
Form 4:
#define DEF_VEC_SAT_S_ADD_FMT_4(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T y = op_2[i]; \
T sum; \
bool overflow = __builtin_add_overflow (x, y, &sum); \
out[i] = !overflow ? sum : x < 0 ? MIN : MAX; \
} \
}
DEF_VEC_SAT_S_ADD_FMT_4 (int8_t, uint8_t, INT8_MIN, INT8_MAX)
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-16.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-13.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-14.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-15.c: New test.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-16.c: New test.
Signed-off-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/gcc-urlifier.cc')
0 files changed, 0 insertions, 0 deletions