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| author | demin.han <demin.han@starfivetech.com> | 2023-12-20 16:15:37 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-12-20 19:19:47 +0800 |
| commit | 3dd6f73a231362a67ff6dee05510bb4fe6253820 (patch) | |
| tree | 595dc10a62002919a62d19606cef9c1601d19511 /gcc/fortran/options.cc | |
| parent | 96e0b513717e25405aee36851d5164aab0d0403a (diff) | |
| download | gcc-3dd6f73a231362a67ff6dee05510bb4fe6253820.zip gcc-3dd6f73a231362a67ff6dee05510bb4fe6253820.tar.gz gcc-3dd6f73a231362a67ff6dee05510bb4fe6253820.tar.bz2 | |
RISC-V: Fix calculation of max live vregs
For the stmt _1 = _2 + _3, assume that _2 or _3 not used after this stmt.
_1 can use same register with _2 or _3 if without early clobber.
Two registers are needed, but current calculation is three.
This patch preserves point 0 for bb entry and excludes its def when
calculates live regs of certain point.
Signed-off-by: demin.han <demin.han@starfivetech.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-costs.cc (max_number_of_live_regs): Fix
max live vregs calc
(preferred_new_lmul_p): Ditto
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Moved to...
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-10.c: ...here.
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul4-4.c: Moved to...
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: ...here.
Signed-off-by: demin.han <demin.han@starfivetech.com>
Diffstat (limited to 'gcc/fortran/options.cc')
0 files changed, 0 insertions, 0 deletions