RISC-V: Provide FP conditional-branch instructions for if-conversion

Do not expand floating-point conditional-branch RTL instructions right
away that use a comparison operation that is either directly available
as a machine conditional-set instruction or is NE, which can be emulated
by EQ.  This is so that if-conversion sees them in their original form
and can produce fewer operations tried in a branchless code sequence
compared to when such an instruction has been already converted to a
sequence of a floating-point conditional-set RTL instruction followed by
an integer conditional-branch RTL instruction.  Split any floating-point
conditional-branch RTL instructions still remaining after reload then.

Adjust the testsuite accordingly: since the middle end uses the inverse
condition internally, an inverse conditional-set instruction may make it
to assembly output and also `cond_move_process_if_block' will be used by
if-conversion rather than `noce_process_if_block', because the latter
function not yet been updated to handle inverted conditions.

	gcc/
	* config/riscv/predicates.md (ne_operator): New predicate.
	* config/riscv/riscv.cc (riscv_insn_cost): Handle branches on a
	floating-point condition.
	* config/riscv/riscv.md (@cbranch<mode>4): Rename expander to...
	(@cbranch<ANYF:mode>4): ... this.  Only expand the RTX via
	`riscv_expand_conditional_branch' for `!signed_order_operator'
	operators, otherwise let it through.
	(*cbranch<ANYF:mode>4, *cbranch<ANYF:mode>4): New insns and
	splitters.

	gcc/testsuite/
	* gcc.target/riscv/movdifge-sfb.c: Reject "if-conversion
	succeeded through" rather than accepting it.
	* gcc.target/riscv/movdifge-thead.c: Likewise.
	* gcc.target/riscv/movdifge-ventana.c: Likewise.
	* gcc.target/riscv/movdifge-zicond.c: Likewise.
	* gcc.target/riscv/movdifgt-sfb.c: Likewise.
	* gcc.target/riscv/movdifgt-thead.c: Likewise.
	* gcc.target/riscv/movdifgt-ventana.c: Likewise.
	* gcc.target/riscv/movdifgt-zicond.c: Likewise.
	* gcc.target/riscv/movdifle-sfb.c: Likewise.
	* gcc.target/riscv/movdifle-thead.c: Likewise.
	* gcc.target/riscv/movdifle-ventana.c: Likewise.
	* gcc.target/riscv/movdifle-zicond.c: Likewise.
	* gcc.target/riscv/movdiflt-sfb.c: Likewise.
	* gcc.target/riscv/movdiflt-thead.c: Likewise.
	* gcc.target/riscv/movdiflt-ventana.c: Likewise.
	* gcc.target/riscv/movdiflt-zicond.c: Likewise.
	* gcc.target/riscv/movsifge-sfb.c: Likewise.
	* gcc.target/riscv/movsifge-thead.c: Likewise.
	* gcc.target/riscv/movsifge-ventana.c: Likewise.
	* gcc.target/riscv/movsifge-zicond.c: Likewise.
	* gcc.target/riscv/movsifgt-sfb.c: Likewise.
	* gcc.target/riscv/movsifgt-thead.c: Likewise.
	* gcc.target/riscv/movsifgt-ventana.c: Likewise.
	* gcc.target/riscv/movsifgt-zicond.c: Likewise.
	* gcc.target/riscv/movsifle-sfb.c: Likewise.
	* gcc.target/riscv/movsifle-thead.c: Likewise.
	* gcc.target/riscv/movsifle-ventana.c: Likewise.
	* gcc.target/riscv/movsifle-zicond.c: Likewise.
	* gcc.target/riscv/movsiflt-sfb.c: Likewise.
	* gcc.target/riscv/movsiflt-thead.c: Likewise.
	* gcc.target/riscv/movsiflt-ventana.c: Likewise.
	* gcc.target/riscv/movsiflt-zicond.c: Likewise.
	* gcc.target/riscv/smax-ieee.c: Also accept FLT.D.
	* gcc.target/riscv/smaxf-ieee.c: Also accept FLT.S.
	* gcc.target/riscv/smin-ieee.c: Also accept FGT.D.
	* gcc.target/riscv/sminf-ieee.c: Also accept FGT.S.

0 files changed, 0 insertions, 0 deletions