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| author | Pan Li <pan2.li@intel.com> | 2024-10-23 16:43:37 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-10-29 22:19:34 +0800 |
| commit | 372060d78715d9a4ab756b1b95796bd04c0be2bf (patch) | |
| tree | cb608a8d06c3cc71f06f8b6ae1d27c212e799f20 /gcc/fortran/error.cc | |
| parent | a0292ddb21475e8fd238e201d3b64f0ab02ace04 (diff) | |
| download | gcc-372060d78715d9a4ab756b1b95796bd04c0be2bf.zip gcc-372060d78715d9a4ab756b1b95796bd04c0be2bf.tar.gz gcc-372060d78715d9a4ab756b1b95796bd04c0be2bf.tar.bz2 | |
RISC-V: Adjust the gather-scatter testcases due to middle-end change
After we have MASK_LEN_STRIDED_LOAD{STORE} in the middle-end, the
strided case need to be adjust for IR check.
The below test suites are passed for this patch:
* The riscv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-1.c:
Adjust IR for MASK_LEN_LOAD check.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_load-2.c:
Ditto.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-1.c:
Ditto but for store.
* gcc.target/riscv/rvv/autovec/gather-scatter/strided_store-2.c:
Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Diffstat (limited to 'gcc/fortran/error.cc')
0 files changed, 0 insertions, 0 deletions