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| author | Richard Earnshaw <rearnsha@arm.com> | 2021-10-21 16:20:49 +0100 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2022-01-20 11:14:43 +0000 |
| commit | facbc2368c8f373a596e7665beb29b96c894bae2 (patch) | |
| tree | e42bd007f26514a712c1bf608b1f515987b1aaa5 /gcc/doc | |
| parent | c471ee0f05d8de576c195996cc3c8ae3ca73d978 (diff) | |
| download | gcc-facbc2368c8f373a596e7665beb29b96c894bae2.zip gcc-facbc2368c8f373a596e7665beb29b96c894bae2.tar.gz gcc-facbc2368c8f373a596e7665beb29b96c894bae2.tar.bz2 | |
arm: Add option for mitigating against Cortex-A CPU erratum for AES
Add a new option -mfix-cortex-a-aes for enabling the Cortex-A AES
erratum work-around and enable it automatically for the affected
products (Cortex-A57 and Cortex-A72).
gcc/ChangeLog:
* config/arm/arm-cpus.in (quirk_aes_1742098): New quirk feature
(ALL_QUIRKS): Add it.
(cortex-a57, cortex-a72): Enable it.
(cortex-a57.cortex-a53, cortex-a72.cortex-a53): Likewise.
* config/arm/arm.opt (mfix-cortex-a57-aes-1742098): New command-line
option.
(mfix-cortex-a72-aes-1655431): New option alias.
* config/arm/arm.cc (arm_option_override): Handle default settings
for AES erratum switch.
* doc/invoke.texi (Arm Options): Document new options.
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 58751c4..67693d6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -812,6 +812,8 @@ Objective-C and Objective-C++ Dialects}. -mtp=@var{name} -mtls-dialect=@var{dialect} @gol -mword-relocations @gol -mfix-cortex-m3-ldrd @gol +-mfix-cortex-a57-aes-1742098 @gol +-mfix-cortex-a72-aes-1655431 @gol -munaligned-access @gol -mneon-for-64bits @gol -mslow-flash-data @gol @@ -21281,6 +21283,15 @@ with overlapping destination and base registers are used. This option avoids generating these instructions. This option is enabled by default when @option{-mcpu=cortex-m3} is specified. +@item -mfix-cortex-a57-aes-1742098 +@itemx -mno-fix-cortex-a57-aes-1742098 +@itemx -mfix-cortex-a72-aes-1655431 +@itemx -mno-fix-cortex-a72-aes-1655431 +Enable (disable) mitigation for an erratum on Cortex-A57 and +Cortex-A72 that affects the AES cryptographic instructions. This +option is enabled by default when either @option{-mcpu=cortex-a57} or +@option{-mcpu=cortex-a72} is specified. + @item -munaligned-access @itemx -mno-unaligned-access @opindex munaligned-access |