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authorAdam Nemet <anemet@caviumnetworks.com>2008-08-01 01:18:16 +0000
committerAdam Nemet <nemet@gcc.gnu.org>2008-08-01 01:18:16 +0000
commitf2d6ca5081ba8fb31b5d03545f45cce12ac67b3f (patch)
tree14f707859af1f88b8b32e8fbfb3ce2f7e2e92e4d /gcc/doc
parent24f9c418761c378444d3bf32a9fe68e328ddf458 (diff)
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config.gcc (mipsisa64*-*-linux*): New configuration.
* config.gcc (mipsisa64*-*-linux*): New configuration. Set ISA to MIPS64r2 for mipsisa64r2*. * config/mips/mips.h (GENERATE_MIPS16E): Update comment. (ISA_MIPS64R2): New macro. (TARGET_CPU_CPP_BUILTINS, MULTILIB_ISA_DEFAULT): Handle it. (ISA_HAS_64BIT_REGS, ISA_HAS_MUL3, ISA_HAS_FP_CONDMOVE, ISA_HAS_8CC, ISA_HAS_FP4, ISA_HAS_PAIRED_SINGLE, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD4_NMSUB4, ISA_HAS_CLZ_CLO, ISA_HAS_ROR, ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX, ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS, ISA_HAS_MXHC1, ISA_HAS_HILO_INTERLOCKS, ISA_HAS_SYNCI, MIN_FPRS_PER_FMT): Return true for ISA_MIPS64R2. (MIPS_ISA_LEVEL_SPEC, ASM_SPEC, LINK_SPEC): Handle -mips64r2. (TARGET_LOONGSON_2E, TARGET_LOONGSON_2F, TARGET_LOONGSON_2EF): Move up to keep list alphabetically sorted. (TUNE_20KC, TUNE_24K, TUNE_74K, TUNE_LOONGSON_2EF): Likewise. * config/mips/mips.c (mips_cpu_info_table): Add default MIPS64r2 processor. * doc/invoke.texi (MIPS Options): Add -mips64r2. (-march=@var{arch}): Add mips64r2. testsuite/ * gcc.target/mips/ext-1.c: New test. From-SVN: r138448
Diffstat (limited to 'gcc/doc')
-rw-r--r--gcc/doc/invoke.texi9
1 files changed, 7 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 33f0018..c2495b3 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -629,7 +629,8 @@ Objective-C and Objective-C++ Dialects}.
@emph{MIPS Options}
@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
--mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
+-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 @gol
+-mips64 -mips64r2 @gol
-mips16 -mno-mips16 -mflip-mips16 @gol
-minterlink-mips16 -mno-interlink-mips16 @gol
-mabi=@var{abi} -mabicalls -mno-abicalls @gol
@@ -11963,7 +11964,7 @@ Generate code that will run on @var{arch}, which can be the name of a
generic MIPS ISA, or the name of a particular processor.
The ISA names are:
@samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
-@samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
+@samp{mips32}, @samp{mips32r2}, @samp{mips64} and @samp{mips64r2}.
The processor names are:
@samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc},
@samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd},
@@ -12065,6 +12066,10 @@ Equivalent to @samp{-march=mips32r2}.
@opindex mips64
Equivalent to @samp{-march=mips64}.
+@item -mips64r2
+@opindex mips64r2
+Equivalent to @samp{-march=mips64r2}.
+
@item -mips16
@itemx -mno-mips16
@opindex mips16