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| author | Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> | 2013-11-18 09:25:21 +0000 |
|---|---|---|
| committer | Ganesh Gopalasubramanian <gganesh@gcc.gnu.org> | 2013-11-18 09:25:21 +0000 |
| commit | ed97ad4709f095da78aa0a4f5653b9509984d579 (patch) | |
| tree | 9f7a7cf7f1b537666804815feb73b7f92593f5da /gcc/doc | |
| parent | 2621c8604391474434d483dace479cb71452f123 (diff) | |
| download | gcc-ed97ad4709f095da78aa0a4f5653b9509984d579.zip gcc-ed97ad4709f095da78aa0a4f5653b9509984d579.tar.gz gcc-ed97ad4709f095da78aa0a4f5653b9509984d579.tar.bz2 | |
AMD bdver4 enablement
From-SVN: r204939
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/extend.texi | 3 | ||||
| -rw-r--r-- | gcc/doc/invoke.texi | 15 |
2 files changed, 13 insertions, 5 deletions
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 599dee3..88eba80 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -10587,6 +10587,9 @@ AMD Family 15h Bulldozer version 2. @item bdver3 AMD Family 15h Bulldozer version 3. +@item bdver4 +AMD Family 15h Bulldozer version 4. + @item btver2 AMD Family 16h CPU. @end table diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index ff4c2ee..a3fdbb5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14529,14 +14529,19 @@ supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) @item bdver2 AMD Family 15h core based CPUs with x86-64 instruction set support. (This -supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, -SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set +supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, +SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) @item bdver3 AMD Family 15h core based CPUs with x86-64 instruction set support. (This -supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, -SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set -extensions. +supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES, +PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and +64-bit instruction set extensions. +@item bdver4 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP, +AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, +SSE4.2, ABM and 64-bit instruction set extensions. @item btver1 CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This |