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| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2012-11-26 12:37:55 +0000 |
|---|---|---|
| committer | Greta Yorsh <gretay@gcc.gnu.org> | 2012-11-26 12:37:55 +0000 |
| commit | e3f9361d493097a0bc70f131feafad0f89867d6e (patch) | |
| tree | e65beb800ddf6448ed8b123d895bfaa71a932afa /gcc/doc | |
| parent | 1dd4fe1fd892458ce29f15f3ca95125a11b2534f (diff) | |
| download | gcc-e3f9361d493097a0bc70f131feafad0f89867d6e.zip gcc-e3f9361d493097a0bc70f131feafad0f89867d6e.tar.gz gcc-e3f9361d493097a0bc70f131feafad0f89867d6e.tar.bz2 | |
sourcebuild.texi: Document arm_v8_vfp_ok.
gcc/
2012-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* doc/sourcebuild.texi: Document arm_v8_vfp_ok.
gcc/testsuite/
2012-11-26 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (check_effective_target_arm_v8_vfp_ok):
New procedure.
(add_options_for_arm_v8_vfp): New procedure.
* gcc.target/arm/vrintaf32.c: New test.
* gcc.target/arm/vrintaf64.c: Likewise.
* gcc.target/arm/vrintmf32.c: Likewise.
* gcc.target/arm/vrintmf64.c: Likewise.
* gcc.target/arm/vrintpf32.c: Likewise.
* gcc.target/arm/vrintpf64.c: Likewise.
* gcc.target/arm/vrintrf32.c: Likewise.
* gcc.target/arm/vrintrf64.c: Likewise.
* gcc.target/arm/vrintxf32.c: Likewise.
* gcc.target/arm/vrintxf64.c: Likewise.
* gcc.target/arm/vrintzf32.c: Likewise.
* gcc.target/arm/vrintzf64.c: Likewise.
From-SVN: r193814
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index ec8263f..0f29326 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1556,6 +1556,10 @@ ARM target generates Thumb-2 code for @code{-mthumb}. ARM target supports @code{-mfpu=vfp -mfloat-abi=softfp}. Some multilibs may be incompatible with these options. +@item arm_v8_vfp_ok +ARM target supports @code{-mfpu=fp-armv8 -mfloat-abi=softfp}. +Some multilibs may be incompatible with these options. + @item arm_prefer_ldrd_strd ARM target prefers @code{LDRD} and @code{STRD} instructions over @code{LDM} and @code{STM} instructions. |