mips.c (mips_class_max_nregs, [...]): New functions.

2002-04-24  Matt Hiller  <hiller@redhat.com>

	* mips.c (mips_class_max_nregs, mips_register_move_cost): New
	functions.
	* mips.h (CLASS_MAX_NREGS, REGISTER_MOVE_COST): Redefine as calls
	of the corresponding functions.
	* mips-protos.h (mips_class_max_nregs, mips_register_move_cost):
	New prototypes.

2002-04-24  Matt Hiller  <hiller@redhat.com>

	* config/mips/mips.h (mips_sw_reg_names): Declare as extern.

	(ALL_COP_ADDITIONAL_REGISTER_NAMES): New macro.
	(FIRST_PSEUDO_REGISTER): Redefine considering coprocessor
	registers, adjust comment accordingly.
	(FIXED_REGISTERS, CALL_USED_REGISTERS, CALL_REALLY_USED_REGISTERS,
	reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS, REGISTER_NAMES,
	DEBUG_REGISTER_NAMES, REG_ALLOC_ORDER): Adjust to include entries
	for coprocessor registers.
	(ADDITIONAL_REGISTER_NAMES): Include
	ALL_COP_ADDITIONAL_REGISTER_NAMES.

	(COP0_REG_FIRST, COP0_REG_LAST, COP0_REG_NUM,
	COP2_REG_FIRST, COP2_REG_LAST, COP2_REG_NUM,
	COP3_REG_FIRST, COP3_REG_LAST, COP3_REG_NUM,
	COP0_REG_P, COP2_REG_P, COP3_REG_P, ALL_COP_REG_P,
	COPNUM_AS_CHAR_FROM_REGNUM, COP_REG_CLASS_P): New macros.

	(mips_char_to_class): Adjust comment to include coprocessor
	constraint letters.

	* config/mips/mips.c (coprocessor_operand, coprocessor2_operand):
	New functions.
	(mips_reg_names, mips_regno_to_class): Include coprocessor
	information.
	(mips_sw_reg_names): Ditto, make non-static.
	(mips_move_1word): Handle moves to and from coprocessor registers.
	(mips_move_2words): Handle moves to and from coprocessor
	registers.
	(mips_class_max_nregs, mips_register_move_cost): Handle
	coprocessor register classes.
	(override_options): Initialize mips_char_to_class and
	mips_hard_regno_mode_ok properly for coprocessor registers.

	* config/mips/mips.md (movdi_internal, movdi_internal2,
	movsi_internal1, movsi_internal2): Add constraint-sets for
	coprocessor registers.
	* testsuite/gcc.c-torture/mipscop-1.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-1.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-2.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-2.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-3.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-3.x: Disable above if target
	isn't mips.
	* testsuite/gcc.c-torture/mipscop-4.c: New testcase.
	* testsuite/gcc.c-torture/mipscop-4.x: Disable above if target
	isn't mips.

	* doc/tm.texi: Document feature.

From-SVN: r52765

1 files changed, 45 insertions, 0 deletions

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index c566c29..f3243b2 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -49,6 +49,7 @@ through the macros defined in the @file{.h} file.
 * Floating Point::      Handling floating point for cross-compilers.
 * Mode Switching::      Insertion of mode-switching instructions.
 * Target Attributes::   Defining target-specific uses of @code{__attribute__}.
+* MIPS Coprocessors::   MIPS coprocessor support and how to customize it.
 * Misc::                Everything else.
 @end menu
 
@@ -8039,6 +8040,50 @@ attributes, @code{false} otherwise.  By default, if a function has a
 target specific attribute attached to it, it will not be inlined.
 @end deftypefn
 
+@node MIPS Coprocessors
+@section Defining coprocessor specifics for MIPS targets.
+@cindex MIPS coprocessor-definition macros
+
+The MIPS specification allows MIPS implementations to have as many as 4
+coprocessors, each with as many as 32 private registers.  gcc supports
+accessing these registers and transferring values between the registers
+and memory using asm-ized variables.  For example:
+
+@smallexample
+  register unsigned int cp0count asm ("c0r1");
+  unsigned int d;
+
+  d = cp0count + 3;
+@end smallexample
+
+(``c0r1'' is the default name of register 1 in coprocessor 0; alternate
+names may be added as described below, or the default names may be
+overridden entirely in @code{SUBTARGET_CONDITIONAL_REGISTER_USAGE}.)
+
+Coprocessor registers are assumed to be epilogue-used; sets to them will
+be preserved even if it does not appear that the register is used again
+later in the function.
+
+Another note: according to the MIPS spec, coprocessor 1 (if present) is
+the FPU.  One accesses COP1 registers through standard mips
+floating-point support; they are not included in this mechanism.
+
+There is one macro used in defining the MIPS coprocessor interface which
+you may want to override in subtargets; it is described below.
+
+@table @code
+
+@item ALL_COP_ADDITIONAL_REGISTER_NAMES
+@findex ALL_COP_ADDITIONAL_REGISTER_NAMES
+A comma-separated list (with leading comma) of pairs describing the
+alternate names of coprocessor registers.  The format of each entry should be
+@smallexample
+@{ @var{alternatename}, @var{register_number}@}
+@end smallexample
+Default: empty.
+
+@end table
+
 @node Misc
 @section Miscellaneous Parameters
 @cindex parameters, miscellaneous