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| author | Chen Liqin <liqin@sunnorth.com.cn> | 2007-04-04 01:49:10 +0000 |
|---|---|---|
| committer | Chen Liqin <liqin@gcc.gnu.org> | 2007-04-04 01:49:10 +0000 |
| commit | c668146359113c30e8c1e5a44153cc0e45f073eb (patch) | |
| tree | 161a48bb545b26b41ec061a8f303dabd808e7160 /gcc/doc | |
| parent | d4c3cb8c5ce69bae3ca3a6d7d3b0f4ce55a0fe7d (diff) | |
| download | gcc-c668146359113c30e8c1e5a44153cc0e45f073eb.zip gcc-c668146359113c30e8c1e5a44153cc0e45f073eb.tar.gz gcc-c668146359113c30e8c1e5a44153cc0e45f073eb.tar.bz2 | |
crti.asm: Change _bss_start to __bss_start.
2007-04-04 Chen Liqin <liqin@sunnorth.com.cn>
* config/score/crti.asm: Change _bss_start to __bss_start.
* config/score/score.h (CONDITIONAL_REGISTER_USAGE): Added.
(OUTGOING_REG_PARM_STACK_SPACE) update.
* config/score/score.opt: add options to make backend support
score5, score5u, score7 and score7d.
* config/score/score.md: Likewise.
* config/score/misc.md: Likewise.
* config/score/mac.md: Likewise.
* doc/invoke.texi: Likewise.
* doc/md.texi: update constraints define.
From-SVN: r123490
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 34 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 14 |
2 files changed, 27 insertions, 21 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e66977a..09f6b67 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -709,9 +709,11 @@ See RS/6000 and PowerPC Options. -mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} @emph{Score Options} -@gccoptlist{-mel -mel @gol +@gccoptlist{-meb -mel @gol +-mnhwloop @gol +-muls @gol -mmac @gol --mscore5u -mscore7} +-mscore5 -mscore5u -mscore7 -mscore7d} @emph{SH Options} @gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol @@ -12924,17 +12926,29 @@ The @var{stack-guard} option can only be used in conjunction with @var{stack-siz These options are defined for Score implementations: @table @gcctabopt -@item -mel -@opindex -mel -Compile code for little endian mode. - @item -meb @opindex meb Compile code for big endian mode. This is the default. +@item -mel +@opindex -mel +Compile code for little endian mode. + +@item -mnhwloop +@opindex -mnhwloop +Disable generate bcnz instruction. + +@item -muls +@opindex -muls +Enable generate unaligned load and store instruction. + @item -mmac @opindex mmac -Enable the use of multiply-accumulate instructions. Disabled by default. +Enable the use of multiply-accumulate instructions. Disabled by default. + +@item -mscore5 +@opindex mscore5 +Specify the SCORE5 as the target architecture. @item -mscore5u @opindex mscore5u @@ -12942,7 +12956,11 @@ Specify the SCORE5U of the target architecture. @item -mscore7 @opindex mscore7 -Specify the SCORE7 of the target architecture. This is the default. +Specify the SCORE7 as the target architecture. This is the default. + +@item -mscore7d +@opindex mscore7d +Specify the SCORE7D as the target architecture. @end table @node SH Options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 01bcb59..2c60ace 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2903,7 +2903,7 @@ cp3 registers. cp1 + cp2 + cp3 registers. @item I -Unsigned 15 bit integer (in the range 0 to 32767). +High 16-bit constant (32-bit constant with 16 LSBs zero). @item J Unsigned 5 bit integer (in the range 0 to 31). @@ -2920,18 +2920,6 @@ Unsigned 14 bit integer (in the range 0 to 16383). @item N Signed 14 bit integer (in the range @minus{}8192 to 8191). -@item O -Signed 15 bit integer (in the range @minus{}16384 to 16383). - -@item P -Signed 12 bit integer (in the range @minus{}2048 to 2047). - -@item J -An integer constant with exactly a single bit set. - -@item Q -An integer constant. - @item Z Any SYMBOL_REF. @end table |