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| author | Yuliang Wang <yuliang.wang@arm.com> | 2019-09-30 16:55:45 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2019-09-30 16:55:45 +0000 |
| commit | c0c2f013906a695b8a02226f119649a370d9e083 (patch) | |
| tree | 6743c5d13bf23522c114e0de5e187c1dade8a1c4 /gcc/doc | |
| parent | dcdd0f055731a8c960a15e5de8715d041d9a7876 (diff) | |
| download | gcc-c0c2f013906a695b8a02226f119649a370d9e083.zip gcc-c0c2f013906a695b8a02226f119649a370d9e083.tar.gz gcc-c0c2f013906a695b8a02226f119649a370d9e083.tar.bz2 | |
[AArch64][SVE] Utilize ASRD instruction for division and remainder
2019-09-30 Yuliang Wang <yuliang.wang@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (sdiv_pow2<mode>3):
New pattern for ASRD.
* config/aarch64/iterators.md (UNSPEC_ASRD): New unspec.
* internal-fn.def (IFN_DIV_POW2): New internal function.
* optabs.def (sdiv_pow2_optab): New optab.
* tree-vect-patterns.c (vect_recog_divmod_pattern):
Modify pattern to support new operation.
* doc/md.texi (sdiv_pow2$var{m3}): Documentation for the above.
* doc/sourcebuild.texi (vect_sdiv_pow2_si):
Document new target selector.
gcc/testsuite/
* gcc.dg/vect/vect-sdiv-pow2-1.c: New test.
* gcc.target/aarch64/sve/asrdiv_1.c: As above.
* lib/target-supports.exp (check_effective_target_vect_sdiv_pow2_si):
Return true for AArch64 with SVE.
From-SVN: r276343
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/md.texi | 11 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 4 |
2 files changed, 15 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index f35fd2b..868016a 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5414,6 +5414,17 @@ op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); where the sign of @samp{narrow} determines whether this is a signed or unsigned operation, and @var{N} is the size of @samp{wide} in bits. +@cindex @code{sdiv_pow2@var{m3}} instruction pattern +@item @samp{sdiv_pow2@var{m3}} +@cindex @code{sdiv_pow2@var{m3}} instruction pattern +@itemx @samp{sdiv_pow2@var{m3}} +Signed division by power-of-2 immediate. Equivalent to: +@smallexample +signed op0, op1; +@dots{} +op0 = op1 / (1 << imm); +@end smallexample + @cindex @code{vec_shl_insert_@var{m}} instruction pattern @item @samp{vec_shl_insert_@var{m}} Shift the elements in vector input operand 1 left one element (i.e.@: diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 9b98f01..5696792 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1446,6 +1446,10 @@ of bytes. Target supports both signed and unsigned multiply-high-with-round-and-scale operations on vectors of half-words. +@item vect_sdiv_pow2_si +Target supports signed division by constant power-of-2 operations +on vectors of 4-byte integers. + @item vect_condition Target supports vector conditional operations. |