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authorTakayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>2022-06-14 12:34:48 +0900
committerMax Filippov <jcmvbkbc@gmail.com>2022-06-15 16:55:36 -0700
commit96518f714e3fab53a966a05b8d48011e27c1a718 (patch)
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xtensa: Document new -mextra-l32r-costs= Xtensa-specific option
gcc/ChangeLog: * doc/invoke.texi: Document -mextra-l32r-costs= option.
Diffstat (limited to 'gcc/doc')
-rw-r--r--gcc/doc/invoke.texi11
1 files changed, 10 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 0eab7e4..60b7b5a 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1474,7 +1474,8 @@ See RS/6000 and PowerPC Options.
-mauto-litpools -mno-auto-litpools @gol
-mtarget-align -mno-target-align @gol
-mlongcalls -mno-longcalls @gol
--mabi=@var{abi-type}}
+-mabi=@var{abi-type} @gol
+-mextra-l32r-costs=@var{cycles}}
@emph{zSeries Options}
See S/390 and zSeries Options.
@@ -33549,6 +33550,14 @@ by 8 registers on entry so that its arguments are found in registers
pointer. Register window is rotated 8 registers back upon return.
When this version of the ABI is enabled the C preprocessor symbol
@code{__XTENSA_WINDOWED_ABI__} is defined.
+
+@item -mextra-l32r-costs=@var{n}
+@opindex mextra-l32r-costs
+Specify an extra cost of instruction RAM/ROM access for @code{L32R}
+instructions, in clock cycles. This affects, when optimizing for speed,
+whether loading a constant from literal pool using @code{L32R} or
+synthesizing the constant from a small one with a couple of arithmetic
+instructions. The default value is 0.
@end table
@node zSeries Options