predicates.md (rx_store_multiple_vector): Reverse order of expected registers.

        * config/rx/predicates.md (rx_store_multiple_vector): Reverse
        order of expected registers.
        (rx_load_multiple_vector): Likewise.
        (rx_rtsd_vector): Likewise.
        * config/rx/rx.c (rx_cpu_type): New variable.
        (rx_print_operand): Fix bug printing 64-bit constant values.
        (rx_emit_stack_pushm): Reverse order of pushed registers.
        (gen_rx_store_vector): Likewise.
        (is_fast_interrupt_func): Only accept "fast_interrupt" as the
        attribute name.
        (is_exception_func): Rename to is_interrupt_func and only accept
        "interrupt" as the attribute name.
        (rx_get_stack_layout): Use new function name.
        (rx_func_attr_inlinable): Likewise.
        (rx_attribute_table): Remove "exception".
        (rx_expand_prologue): If necessary push the accumulator register
        in the prologue of interrupt functions.
        (rx_expand_epilogue): If necessary pop the accumulator.
        (rx_builtins): Add RX_BUILTIN_MVTIPL.
        (rx_expand_builtin_stz): Remove.
        (rx_expand_builtin_mvtipl): New function.
        (rx_init_builtins): Handle RX_BUILTIN_MVTIPL.
        (rx_expand_builtin): Likewise.
        (rx_enable_fpu): New variable.
        (rx_handle_option): Handle -fpu, -nofpu, -mcpu and -patch.
        * config/rx/rx.h (TARGET_CPU_CPP_BUILTINS): Assert machine based
        on rx_cpu_type.  Define __RX_FPU_INSNS__ if FPU insns are allowed.
        (enum rx_cpu_types): Define.
        (ASM_SPEC): Pass -m32bit-doubles on to assembler.
        (INCOMING_FRAME_SP_OFFSET): Define.
        (ARG_POINTER_CFA_OFFSET): Define.
        (FRAME_POINTER_CFA_OFFSET): Define.
        (OVERRIDE_OPTIONS): Enable fast math if RX FPU insns are enabled.
        (ALLOW_RX_FPU_INSNS): Define.
        * config/rx/rx.md: Test ALLOW_RX_FPU_INSNS instead of
        fast_math_flags_set_p.
        (UNSPEC_BUILTIN_MVTIPL): Define.
        (revl): Rename to bswapsi2.
        (bswaphi2): New pattern.
        (mvtachi): Mark as volatile because it uses a register unknown to
        GCC.
        (mvtaclo): Likewise.
        (racw): Likewise.
        (mvtc): Remove clobber of cc0.
        (mvtcp): Delete.
        (opecp): Delete.
        * config/rx/rx.opt (mieee): Remove.
        (fpu): Add.
        (nofpu): Add.
        (mcpu=): Add.
        (patch=): Add.
        (msave-acc-in-interrupts): Add.
        * config/rx/t-rx (MULTILIB_OPTIONS): Change default to 64bit
        doubles.
        (MULTILIB_DIRS): Likewise.
        (MULTILIB_MATCHES): Treat -fpu as an alias for -m32bit-doubles.
        * doc/extend.texi: Remove description of "exception" function
        attribute.
        * doc/invoke.texi: Document -fpu, -nofpu, -mcpu=, -patch= and
        -msave-acc-in-interrupts options.

        * gcc.target/rx/builtins,c: Remove redundant tests.
        Add test of MVTIPL instruction.
        * gcc.target/rx/interrupts.c: Use fast_interrupt and interrupt
        function attributes.  Add -msave-acc-in-interrupts option to the
        command line.

Co-Authored-By: Kevin Buettner <kevinb@redhat.com>

From-SVN: r153853

2 files changed, 35 insertions, 10 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index cb764c6..bfcc5fb 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -2270,13 +2270,6 @@ on data in the eight bit data area.  Note the eight bit data area is limited to
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
-@item exception
-@cindex exception handler functions on the RX processor
-Use this attribute on the RX to indicate that the specified function
-is an exception handler.  The compiler will generate function entry and
-exit sequences suitable for use in an exception handler when this
-attribute is present.
-
 @item exception_handler
 @cindex exception handler functions on the Blackfin processor
 Use this attribute on the Blackfin to indicate that the specified function
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 93d87cc..ed652ec 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -784,14 +784,16 @@ See RS/6000 and PowerPC Options.
 -msdata=@var{opt}  -mvxworks  -G @var{num}  -pthread}
 
 @emph{RX Options}
-@gccoptlist{-m64bit-doubles  -m32bit-doubles  -mieee  -mno-ieee@gol
+@gccoptlist{-m64bit-doubles  -m32bit-doubles  -fpu  -nofpu@gol
+-mcpu= -patch=@gol
 -mbig-endian-data -mlittle-endian-data @gol
 -msmall-data @gol
 -msim  -mno-sim@gol
 -mas100-syntax -mno-as100-syntax@gol
 -mrelax@gol
 -mmax-constant-size=@gol
--mint-register=}
+-mint-register=@gol
+-msave-acc-in-interrupts}
 
 @emph{S/390 and zSeries Options}
 @gccoptlist{-mtune=@var{cpu-type}  -march=@var{cpu-type} @gol
@@ -15408,16 +15410,37 @@ These @option{-m} options are defined for RX implementations:
 @table @gcctabopt
 @item -m64bit-doubles
 @itemx -m32bit-doubles
+@itemx -fpu
+@itemx -nofpu
 @opindex m64bit-doubles
 @opindex m32bit-doubles
+@opindex fpu
+@opindex nofpu
 Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
 or 32-bits (@option{-m32bit-doubles}) in size.  The default is
-@option{-m32bit-doubles}.  @emph{Note} the RX's hardware floating
+@option{-m64bit-doubles}.  @emph{Note} the RX's hardware floating
 point instructions are only used for 32-bit floating point values, and
 then only if @option{-ffast-math} has been specified on the command
 line.  This is because the RX FPU instructions do not properly support
 denormal (or sub-normal) values.
 
+The options @option{-fpu} and @option{-nofpu} have been provided at
+the request of Rensas for compatibility with their toolchain.  The
+@option{-mfpu} option enables the use of RX FPU instructions by
+selecting 32-bit doubles and enabling unsafe math optimizations.  The
+@option{-mnofpu} option disables the use of RX FPU instructions, even
+if @option{-m32bit-doubles} is active and unsafe math optimizations
+have been enabled.
+
+@item -mcpu=@var{name}
+@itemx -patch=@var{name}
+@opindex -mcpu
+@opindex -patch
+Selects the type of RX CPU to be targeted.  Currently on two types are
+supported, the generic @var{RX600} and the specific @var{RX610}.  The
+only difference between them is that the @var{RX610} does not support
+the @code{MVTIPL} instruction.
+
 @item -mbig-endian-data
 @itemx -mlittle-endian-data
 @opindex mbig-endian-data
@@ -15493,6 +15516,15 @@ of fast interrupt handlers.  A value of 2 reserves @code{r13} and
 @code{r12}.  A value of 3 reserves @code{r13}, @code{r12} and
 @code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
 A value of 0, the default, does not reserve any registers.
+
+@item -msave-acc-in-interrupts
+@opindex msave-acc-in-interrupts
+Specifies that interrupt handler functions should preserve the
+accumulator register.  This is only necessary if normal code might use
+the accumulator register, for example because it performs 64-bit
+multiplications.  The default is to ignore the accumulator as this
+makes the interrupt handlers faster.
+
 @end table
 
 @emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}