neon.ml (opcode): Add Vrintn, Vrinta, Vrintp, Vrintm, Vrintz to type.

gcc/ChangeLog

2012-12-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/neon.ml (opcode): Add Vrintn, Vrinta, Vrintp, Vrintm,
	Vrintz to type.
	(type features): Add Requires_arch type constructor.
	(ops): Define Vrintn, Vrinta, Vrintp, Vrintm, Vrintz features.
	* config/arm/neon-docgen.ml (intrinsic_groups): Define Vrintn,
	Vrinta, Vrintp, Vrintm, Vrintz, Vrintx.
	* config/arm/neon-testgen.ml (effective_target): Define check for 
	Requires_arch 8.
	* config/arm/neon-gen.ml 
	(print_feature_test_start): Handle Requires_arch.
	(print_feature_test_end): Likewise.
	Add 2012 to Copyright notice.
	* doc/arm-neon-intrinsics.texi: Regenerate.
	* config/arm/arm_neon.h: Regenerate.

gcc/testsuite/ChangeLog

2012-12-10  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* gcc.target/arm/neon/vrndaf32.c: New test.
	* gcc.target/arm/neon/vrndqaf32.c: Likewise.
	* gcc.target/arm/neon/vrndf32.c: Likewise.
	* gcc.target/arm/neon/vrndqf32.c: Likewise.
	* gcc.target/arm/neon/vrndmf32.c: Likewise.
	* gcc.target/arm/neon/vrndqmf32.c: Likewise.
	* gcc.target/arm/neon/vrndnf32.c: Likewise.
	* gcc.target/arm/neon/vrndqnf32.c: Likewise.
	* gcc.target/arm/neon/vrndpf32.c: Likewise.
	* gcc.target/arm/neon/vrndqpf32.c: Likewise.

From-SVN: r194353

1 files changed, 112 insertions, 32 deletions

diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi
index 14e6264..4b0289a 100644
--- a/gcc/doc/arm-neon-intrinsics.texi
+++ b/gcc/doc/arm-neon-intrinsics.texi
@@ -1004,6 +1004,86 @@
 
 
 
+@subsubsection Round to integral (to nearest, ties to even)
+
+@itemize @bullet
+@item float32x2_t vrndn_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrndqn_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Round to integral (to nearest, ties away from zero)
+
+@itemize @bullet
+@item float32x2_t vrnda_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrndqa_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Round to integral (towards +Inf)
+
+@itemize @bullet
+@item float32x2_t vrndp_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrndqp_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Round to integral (towards -Inf)
+
+@itemize @bullet
+@item float32x2_t vrndm_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrndqm_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
+@subsubsection Round to integral (towards 0)
+
+@itemize @bullet
+@item float32x2_t vrnd_f32 (float32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{d0}, @var{d0}}
+@end itemize
+
+
+@itemize @bullet
+@item float32x4_t vrndq_f32 (float32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{q0}, @var{q0}}
+@end itemize
+
+
+
+
 @subsubsection Subtraction
 
 @itemize @bullet
@@ -7218,12 +7298,6 @@
 @subsubsection Transpose elements
 
 @itemize @bullet
-@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
-@end itemize
-
-
-@itemize @bullet
 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
 @end itemize
@@ -7236,38 +7310,44 @@
 
 
 @itemize @bullet
-@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
+@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
+@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
+@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
-@*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
+@item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
-@*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
+@item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
@@ -7330,12 +7410,6 @@
 @subsubsection Zip elements
 
 @itemize @bullet
-@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
-@end itemize
-
-
-@itemize @bullet
 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
 @end itemize
@@ -7348,38 +7422,44 @@
 
 
 @itemize @bullet
-@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
+@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
+@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
+@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
+@end itemize
+
+
+@itemize @bullet
+@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
+@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
-@*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
+@item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
 @itemize @bullet
-@item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
-@*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
+@item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
+@*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
 @end itemize
 
 
@@ -7939,13 +8019,13 @@
 
 @itemize @bullet
 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
-@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
 @end itemize
 
 
 @itemize @bullet
 @item int64x2_t vld1q_dup_s64 (const int64_t *)
-@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
+@*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
 @end itemize