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| author | Uros Bizjak <ubizjak@gmail.com> | 2007-03-14 08:47:32 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2007-03-14 08:47:32 +0100 |
| commit | 8c5fd59f94de0dd09cd451c532fe746dab52dfca (patch) | |
| tree | 8a061b678873e93e0f03fdff633af18b802c90bb /gcc/doc | |
| parent | e31657e8129711f53f3fd09d846b54bd1b5cfb39 (diff) | |
| download | gcc-8c5fd59f94de0dd09cd451c532fe746dab52dfca.zip gcc-8c5fd59f94de0dd09cd451c532fe746dab52dfca.tar.gz gcc-8c5fd59f94de0dd09cd451c532fe746dab52dfca.tar.bz2 | |
invoke.texi (i386 and x86-64 Options): Clarify -msahf option.
* doc/invoke.texi (i386 and x86-64 Options): Clarify -msahf option.
From-SVN: r122910
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d5a5da5..60122e0 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10091,11 +10091,12 @@ atomic built-in functions: see @ref{Atomic Builtins} for details. @item -msahf @opindex -msahf -This option will enable GCC to use SAHF instruction in generated code. Early -Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 -until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are -load and store instructions, respectively, for certain status flags. These -instructions are used for virtualization and floating-point condition handling. +This option will enable GCC to use SAHF instruction in generated 64-bit code. +Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported +by AMD64 until introduction of Pentium 4 G1 step in December 2005. LAHF and +SAHF are load and store instructions, respectively, for certain status flags. +In 64-bit mode, SAHF instruction is used to optimize @code{fmod}, @code{drem} +or @code{remainder} built-in functions: see @ref{Other Builtins} for details. @item -mpush-args @itemx -mno-push-args |