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| author | David S. Miller <davem@davemloft.net> | 2012-11-15 21:24:22 +0000 |
|---|---|---|
| committer | David S. Miller <davem@gcc.gnu.org> | 2012-11-15 13:24:22 -0800 |
| commit | 8b98b5fd9f9e4edb38a6b7eeb91b5a77ad91d95c (patch) | |
| tree | f03d2f8dce9c22de2316eabb57bfd128e7c91f42 /gcc/doc | |
| parent | 2bf33cdb91a46f5c8ead75a57ec11766f8e6863e (diff) | |
| download | gcc-8b98b5fd9f9e4edb38a6b7eeb91b5a77ad91d95c.zip gcc-8b98b5fd9f9e4edb38a6b7eeb91b5a77ad91d95c.tar.gz gcc-8b98b5fd9f9e4edb38a6b7eeb91b5a77ad91d95c.tar.bz2 | |
Add support for sparc fused compare-and-branch.
gcc/
2012-11-15 David S. Miller <davem@davemloft.net>
* configure.ac: Add check for assembler SPARC4 instruction
support.
* configure: Rebuild.
* config.in: Add HAVE_AS_SPARC4 section.
* config/sparc/sparc.opt (mcbcond): New option.
* doc/invoke.texi: Document it.
* config/sparc/constraints.md: New constraint 'A' for 5-bit signed
immediates.
* doc/md.texi: Document it.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_CBCOND.
(sparc_option_override): Likewise.
(emit_cbcond_insn): New function.
(emit_conditional_branch_insn): Call it.
(emit_cbcond_nop): New function.
(output_ubranch): Use cbcond, remove label arg.
(output_cbcond): New function.
* config/sparc/sparc-protos.h (output_ubranch): Update.
(output_cbcond): Declare it.
(emit_cbcond_nop): Likewise.
* config/sparc/sparc.md (type attribute): New types 'cbcond'
and uncond_cbcond.
(emit_cbcond_nop): New attribute.
(length attribute): Handle cbcond and uncond_cbcond.
(in_call_delay attribute): Reject cbcond and uncond_cbcond.
(in_branch_delay attribute): Likewise.
(in_uncond_branch_delay attribute): Likewise.
(in_annul_branch_delay attribute): Likewise.
(*cbcond_sp32, *cbcond_sp64): New insn patterns.
(jump): Rewrite into an expander.
(*jump_ubranch, *jump_cbcond): New patterns.
* config/sparc/niagara4.md: Match 'cbcond' in 'n4_cti'.
* config/sparc/sparc.h (AS_NIAGARA4_FLAG): New macro, use it
when target default is niagara4.
(SPARC_SIMM5_P): Define.
* config/sparc/sol2.h (AS_SPARC64_FLAG): Adjust.
(AS_SPARC32_FLAG): Define.
(ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC): Use
AS_NIAGARA4_FLAG as needed.
From-SVN: r193543
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 10 | ||||
| -rw-r--r-- | gcc/doc/md.texi | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e019e3d..d5d5658 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -929,6 +929,7 @@ See RS/6000 and PowerPC Options. -munaligned-doubles -mno-unaligned-doubles @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol +-mcbcond -mno-cbcond @gol -mfmaf -mno-fmaf -mpopc -mno-popc @gol -mfix-at697f} @@ -19153,6 +19154,15 @@ default is @option{-mvis3} when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting @option{-mvis3} also sets @option{-mvis2} and @option{-mvis}. +@item -mcbcond +@itemx -mno-cbcond +@opindex mcbcond +@opindex mno-cbcond +With @option{-mcbcond}, GCC generates code that takes advantage of +compare-and-branch instructions, as defined in the Sparc Architecture 2011. +The default is @option{-mcbcond} when targeting a cpu that supports such +instructions, such as niagara-4 and later. + @item -mpopc @itemx -mno-popc @opindex mpopc diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index eb6ba91..396bf43 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3222,6 +3222,9 @@ when the Visual Instruction Set is available. @item C The constant all-ones, for floating-point. +@item A +Signed 5-bit constant + @item D A vector constant |