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| author | Igor Zamyatin <igor.zamyatin@intel.com> | 2013-06-11 09:40:26 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2013-06-11 09:40:26 +0000 |
| commit | 77cea46edbb0b526aa04e4bee9be85103de60fb2 (patch) | |
| tree | fd3593313657b1e5cbae094d77d6e19178107f04 /gcc/doc | |
| parent | 888f0920b96e12a50b48b3c44f08c78906200083 (diff) | |
| download | gcc-77cea46edbb0b526aa04e4bee9be85103de60fb2.zip gcc-77cea46edbb0b526aa04e4bee9be85103de60fb2.tar.gz gcc-77cea46edbb0b526aa04e4bee9be85103de60fb2.tar.bz2 | |
invoke.texi (core-avx2): Document.
* doc/invoke.texi (core-avx2): Document.
(slm): Likewise.
(atom): Updated with MOVBE.
From-SVN: r199943
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index b7b32f7..dd82880 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13833,10 +13833,19 @@ Intel Core CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. +@item core-avx2 +Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA, BMI, BMI2 +and F16C instruction set support. + @item atom -Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 +Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3 instruction set support. +@item slm +Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, +SSE4.1 and SSE4.2 instruction set support. + @item k6 AMD K6 CPU with MMX instruction set support. |