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| author | Claudiu Zissulescu <claziss@gmail.com> | 2022-07-18 15:07:00 +0300 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gmail.com> | 2022-07-18 15:45:20 +0300 |
| commit | 7501eec65c60701f72621d04eeb5342bad2fe4fb (patch) | |
| tree | e8c98397915d2217a334ad84a1479c9670013376 /gcc/doc | |
| parent | 87f46a16ec05beb51439f55a4d3c36d64b95b00f (diff) | |
| download | gcc-7501eec65c60701f72621d04eeb5342bad2fe4fb.zip gcc-7501eec65c60701f72621d04eeb5342bad2fe4fb.tar.gz gcc-7501eec65c60701f72621d04eeb5342bad2fe4fb.tar.bz2 | |
arc: Add ARCHS release 310a tune variant.
Add mtune and mcpu options for ARCHS release 310a type CPU. The
mtune=release31a is designed to be used as an alternative to the
mcpu=hs4x_rel31 option.
ARCHS4x release 31a uses DSP instructions which are implemented a bit
different than mpy9. Hence, use safer mpy2 option.
gcc/
* config/arc/arc-arch.h (arc_tune_attr): Add
ARC_TUNE_ARCHS4X_REL31A variant.
* config/arc/arc.cc (arc_override_options): Tune options for
release 310a.
(arc_sched_issue_rate): Use correct enum.
(arc600_corereg_hazard): Textual change.
(arc_hazard): Add release 310a tunning.
* config/arc/arc.md (tune): Update and take into consideration new
tune option.
(tune_dspmpy): Likewise.
(tune_store): New attribute.
* config/arc/arc.opt (mtune): New tune option.
* config/arc/arcHS4x.md (hs4x_brcc0, hs4x_brcc1): New cpu units.
(hs4x_brcc_op): New instruction rezervation.
(hs4x_data_store_1_op): Likewise.
* config/arc/arc-cpus.def (hs4x_rel31): New cpu variant.
* config/arc/arc-tables.opt: Regenerate.
* config/arc/t-multilib: Likewise.
* doc/invoke.texi (ARC): Update mcpu and tune sections.
Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 84d6f0f..94fe57a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -20053,6 +20053,15 @@ Compile for ARC HS38 CPU. @item hs38_linux Compile for ARC HS38 CPU with all hardware extensions on. +@item hs4x +Compile for ARC HS4x CPU. + +@item hs4xd +Compile for ARC HS4xD CPU. + +@item hs4x_rel31 +Compile for ARC HS4x CPU release 3.10a. + @item arc600_norm Compile for ARC 600 CPU with @code{norm} instructions enabled. @@ -20662,6 +20671,13 @@ Tune for ARC725D CPU. @item ARC750D Tune for ARC750D CPU. +@item core3 +Tune for ARCv2 core3 type CPU. This option enable usage of +@code{dbnz} instruction. + +@item release31a +Tune for ARC4x release 3.10a. + @end table @item -mmultcost=@var{num} |