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| author | Joseph Myers <joseph@codesourcery.com> | 2006-03-14 00:29:07 +0000 |
|---|---|---|
| committer | Joseph Myers <jsm28@gcc.gnu.org> | 2006-03-14 00:29:07 +0000 |
| commit | 716019c0ad646715c24467a80bf0595a1a2ad7cb (patch) | |
| tree | daec867ae253bd094bdc807e9a74b7a29b03ca5c /gcc/doc | |
| parent | a14df7dabe7ede95e34d726741524031746f563c (diff) | |
| download | gcc-716019c0ad646715c24467a80bf0595a1a2ad7cb.zip gcc-716019c0ad646715c24467a80bf0595a1a2ad7cb.tar.gz gcc-716019c0ad646715c24467a80bf0595a1a2ad7cb.tar.bz2 | |
rs6000.opt (mdlmzb): New option.
* config/rs6000/rs6000.opt (mdlmzb): New option.
(msched-prolog, msched-epilog): Use Var not Mask.
* doc/invoke.texi (-mdlmzb): Document.
* config/rs6000/rs6000.c (TARGET_DEFAULT_TARGET_FLAGS): Remove
MASK_SCHED_PROLOG.
(rs6000_override_options): Enable -mdlmzb for 405 and 440.
* config/rs6000/rs6000.md: Add dlmzb support for 405 and 440.
testsuite:
* gcc.target/powerpc/405-dlmzb-strlen-1.c,
gcc.target/powerpc/440-dlmzb-strlen-1.c: New tests.
From-SVN: r112040
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c1de501..f11214f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -670,6 +670,7 @@ See RS/6000 and PowerPC Options. -mspe=yes -mspe=no @gol -mvrsave -mno-vrsave @gol -mmulhw -mno-mulhw @gol +-mdlmzb -mno-dlmzb @gol -mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol -mprototype -mno-prototype @gol -msim -mmvme -mads -myellowknife -memb -msdata @gol @@ -11106,7 +11107,7 @@ following options: @option{-maltivec}, @option{-mfprnd}, @option{-mhard-float}, @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics}, @option{-mpopcntb}, @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64}, @option{-mpowerpc-gpopt}, -@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}. +@option{-mpowerpc-gfxopt}, @option{-mstring}, @option{-mmulhw}, @option{dlmzb}. The particular options set for any particular CPU will vary between compiler versions, depending on what setting seems to produce optimal code for that CPU; @@ -11370,6 +11371,14 @@ multiply-accumulate instructions on the IBM 405 and 440 processors. These instructions are generated by default when targetting those processors. +@item -mdlmzb +@itemx -mno-dlmzb +@opindex mdlmzb +@opindex mno-dlmzb +Generate code that uses (does not use) the string-search @samp{dlmzb} +instruction on the IBM 405 and 440 processors. This instruction is +generated by default when targetting those processors. + @item -mno-bit-align @itemx -mbit-align @opindex mno-bit-align |