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| author | Uros Bizjak <ubizjak@gmail.com> | 2007-03-13 22:18:33 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2007-03-13 22:18:33 +0100 |
| commit | 5be6cb59b3e5ab7b69534841be42f2d6e9fb1340 (patch) | |
| tree | 6b2026da7067b0c4a55a08b49268a5b8ff8b866f /gcc/doc | |
| parent | d265b0b1c24d13c3dfdf830877fa8edf87e8c15d (diff) | |
| download | gcc-5be6cb59b3e5ab7b69534841be42f2d6e9fb1340.zip gcc-5be6cb59b3e5ab7b69534841be42f2d6e9fb1340.tar.gz gcc-5be6cb59b3e5ab7b69534841be42f2d6e9fb1340.tar.bz2 | |
i386.opt (mcx16, msahf): New options.
* config/i386/i386.opt (mcx16, msahf): New options.
* config/i386/i386.c (x86_cmpxchg16b, x86_sahf): Remove.
(ix86_tune_features) [X86_TUNE_USE_SAHF]: Enable for m_GENERIC.
* config/i386/driver-i386.c (bit_LAHF_LM): New define.
(host_detect_local_cpu): Detect cx16 and lahf_lm cpuid bits.
Output -mcx16 and -msahf options when corresponding bit is set.
* doc/invoke.texi (i386 and x86-64 Options): Document -mcx16
and -msahf options.
testsuite/ChangeLog
* testsuite/gcc.target/i386/cmpxchg16b-1.c: New test.
From-SVN: r122884
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 61e82c30..d5a5da5 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -543,7 +543,7 @@ Objective-C and Objective-C++ Dialects}. -masm=@var{dialect} -mno-fancy-math-387 @gol -mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol -mno-wide-multiply -mrtd -malign-double @gol --mpreferred-stack-boundary=@var{num} @gol +-mpreferred-stack-boundary=@var{num} -mcx16 -msahf @gol -mmmx -msse -msse2 -msse3 -mssse3 -msse4a -m3dnow -mpopcnt -mabm @gol -mthreads -mno-align-stringops -minline-all-stringops @gol -mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol @@ -10081,6 +10081,22 @@ supported architecture, using the appropriate flags. In particular, the file containing the CPU detection code should be compiled without these options. +@item -mcx16 +@opindex -mcx16 +This option will enable GCC to use CMPXCHG16B instruction in generated code. +CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) +data types. This is useful for high resolution counters that could be updated +by multiple processors (or cores). This instruction is generated as part of +atomic built-in functions: see @ref{Atomic Builtins} for details. + +@item -msahf +@opindex -msahf +This option will enable GCC to use SAHF instruction in generated code. Early +Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 +until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are +load and store instructions, respectively, for certain status flags. These +instructions are used for virtualization and floating-point condition handling. + @item -mpush-args @itemx -mno-push-args @opindex mpush-args |