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| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2016-01-04 18:22:52 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@gcc.gnu.org> | 2016-01-04 18:22:52 +0000 |
| commit | 4e8a3a35d8b74ba629dfb0d52cf6296a84cc9a6e (patch) | |
| tree | 848b6ddea1ebae2f393c4af0fd868bf8f235dd51 /gcc/doc | |
| parent | f29fa917a5d0e7380f0a1d78a766f09689280293 (diff) | |
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constraints.md (wo constraint): New constraint for ISA 3.0 (power9).
[gcc]
2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/constraints.md (wo constraint): New constraint for
ISA 3.0 (power9).
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add support
for wo constraint.
(rs6000_init_hard_regno_mode_ok): Likewise.
* config/rs6000/rs6000.h (r6000_reg_class_enum): Add support for
wo constraint.
* config/rs6000/altivec.md (altivec_vperm_<mode>): Clean up vperm
expanders not to have constraints. Add support for ISA 3.0 xxperm
instruction. Add support for fusing xxlor with xxperm.
(altivec_vperm_<mode>_internal): Likewise.
(altivec_vperm_v8hiv16qi): Likewise.
(altivec_vperm_<mode>v16q): Likewise.
(altivec_vperm_<mode>_uns): Likewise.
(vperm_v8hiv4si): Likewise.
(vperm_v16qiv8hi): Likewise.
* doc/md.texi (RS/6000 constraints): Document wo constraint.
[gcc/testsuite]
2016-01-04 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p9-permute.c: New test for xxperm code
generation.
From-SVN: r232060
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/md.texi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 6dc43db..faf3910 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3102,8 +3102,8 @@ Any VSX register if the -mvsx option was used or NO_REGS. When using any of the register constraints (@code{wa}, @code{wd}, @code{wf}, @code{wg}, @code{wh}, @code{wi}, @code{wj}, @code{wk}, -@code{wl}, @code{wm}, @code{wp}, @code{wq}, @code{ws}, @code{wt}, -@code{wu}, @code{wv}, @code{ww}, or @code{wy}) +@code{wl}, @code{wm}, @code{wo}, @code{wp}, @code{wq}, @code{ws}, +@code{wt}, @code{wu}, @code{wv}, @code{ww}, or @code{wy}) that take VSX registers, you must use @code{%x<n>} in the template so that the correct register is used. Otherwise the register number output in the assembly file will be incorrect if an Altivec register @@ -3175,6 +3175,9 @@ VSX register if direct move instructions are enabled, or NO_REGS. @item wn No register (NO_REGS). +@item wo +VSX register to use for ISA 3.0 vector instructions, or NO_REGS. + @item wp VSX register to use for IEEE 128-bit floating point TFmode, or NO_REGS. |