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author | Uros Bizjak <uros@gcc.gnu.org> | 2016-05-22 19:20:10 +0200 |
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committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-05-22 19:20:10 +0200 |
commit | 41a6c071413f59fb54484202b565b93afe75684a (patch) | |
tree | 79de3076a968de2196eaf488054b9afdde954a9c /gcc/doc | |
parent | af120161421cdc935ff98a0e5038775f22a1ca90 (diff) | |
download | gcc-41a6c071413f59fb54484202b565b93afe75684a.zip gcc-41a6c071413f59fb54484202b565b93afe75684a.tar.gz gcc-41a6c071413f59fb54484202b565b93afe75684a.tar.bz2 |
revert: re PR target/70738 (Add -mgeneral-regs-only option)
Revert:
gcc/
PR target/70738
* common/config/i386/i386-common.c
(OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET): New.
(ix86_handle_option): Disable MPX, MMX, SSE and x87 instructions
for -mgeneral-regs-only.
* config/i386/i386.c (ix86_option_override_internal): Don't
enable x87 instructions if only the general registers are
allowed.
* config/i386/i386.opt: Add -mgeneral-regs-only.
* doc/invoke.texi: Document -mgeneral-regs-only.
gcc/testsuite/
PR target/70738
* gcc.target/i386/pr70738-1.c: Likewise.
* gcc.target/i386/pr70738-2.c: Likewise.
* gcc.target/i386/pr70738-3.c: Likewise.
* gcc.target/i386/pr70738-4.c: Likewise.
* gcc.target/i386/pr70738-5.c: Likewise.
* gcc.target/i386/pr70738-6.c: Likewise.
* gcc.target/i386/pr70738-7.c: Likewise.
* gcc.target/i386/pr70738-8.c: Likewise.
* gcc.target/i386/pr70738-9.c: Likewise.
From-SVN: r236570
Diffstat (limited to 'gcc/doc')
-rw-r--r-- | gcc/doc/invoke.texi | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 926e1e6..f3d087f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1172,7 +1172,7 @@ See RS/6000 and PowerPC Options. -msse2avx -mfentry -mrecord-mcount -mnop-mcount -m8bit-idiv @gol -mavx256-split-unaligned-load -mavx256-split-unaligned-store @gol -malign-data=@var{type} -mstack-protector-guard=@var{guard} @gol --mmitigate-rop -mgeneral-regs-only} +-mmitigate-rop} @emph{x86 Windows Options} @gccoptlist{-mconsole -mcygwin -mno-cygwin -mdll @gol @@ -24264,12 +24264,6 @@ opcodes, to mitigate against certain forms of attack. At the moment, this option is limited in what it can do and should not be relied on to provide serious protection. -@item -mgeneral-regs-only -@opindex mgeneral-regs-only -Generate code that uses only the general-purpose registers. This -prevents the compiler from using floating-point, vector, mask and bound -registers. - @end table These @samp{-m} switches are supported in addition to the above |