Support Intel SM4

gcc/ChangeLog:

	* common/config/i386/cpuinfo.h (get_available_features):
	Detech SM4.
	* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SM4_SET,
	OPTION_MASK_ISA2_SM4_UNSET): New.
	(OPTION_MASK_ISA2_AVX_UNSET): Add SM4.
	(ix86_handle_option): Handle -msm4.
	* common/config/i386/i386-cpuinfo.h (enum processor_features):
	Add FEATURE_SM4.
	* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
	sm4.
	* config.gcc: Add sm4intrin.h.
	* config/i386/cpuid.h (bit_SM4): New.
	* config/i386/i386-builtin.def (BDESC): Add new builtins.
	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
	__SM4__.
	* config/i386/i386-isa.def (SM4): Add DEF_PTA(SM4).
	* config/i386/i386-options.cc (isa2_opts): Add -msm4.
	(ix86_valid_target_attribute_inner_p): Handle sm4.
	* config/i386/i386.opt: Add option -msm4.
	* config/i386/immintrin.h: Include sm4intrin.h
	* config/i386/sse.md (vsm4key4_<mode>): New define insn.
	(vsm4rnds4_<mode>): Ditto.
	* doc/extend.texi: Document sm4.
	* doc/invoke.texi: Document -msm4.
	* doc/sourcebuild.texi: Document target sm4.
	* config/i386/sm4intrin.h: New file.

gcc/testsuite/ChangeLog:

	* g++.dg/other/i386-2.C: Add -msm4.
	* g++.dg/other/i386-3.C: Ditto.
	* gcc.target/i386/funcspec-56.inc: Add new target attribute.
	* gcc.target/i386/sse-12.c: Add -msm4.
	* gcc.target/i386/sse-13.c: Ditto.
	* gcc.target/i386/sse-14.c: Ditto.
	* gcc.target/i386/sse-22.c: Add sm4.
	* gcc.target/i386/sse-23.c: Ditto.
	* lib/target-supports.exp (check_effective_target_sm4): New.
	* gcc.target/i386/sm4-1.c: New test.
	* gcc.target/i386/sm4-check.h: Ditto.
	* gcc.target/i386/sm4key4-2.c: Ditto.
	* gcc.target/i386/sm4rnds4-2.c: Ditto.

3 files changed, 14 insertions, 3 deletions

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 7086ca9..5e20c83 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7178,6 +7178,11 @@ Enable/disable the generation of the SM3 instructions.
 @itemx no-sha512
 Enable/disable the generation of the SHA512 instructions.
 
+@cindex @code{target("sm4")} function attribute, x86
+@item sm4
+@itemx no-sm4
+Enable/disable the generation of the SM4 instructions.
+
 @cindex @code{target("cld")} function attribute, x86
 @item cld
 @itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 433ccf3..dd28320 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options.
 -mrdseed  -msgx -mavx512vp2intersect -mserialize -mtsxldtrk
 -mamx-tile  -mamx-int8  -mamx-bf16 -muintr -mhreset -mavxvnni
 -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
--mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512
+-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4
 -mcldemote  -mms-bitfields  -mno-align-stringops  -minline-all-stringops
 -minline-stringops-dynamically  -mstringop-strategy=@var{alg}
 -mkl -mwidekl
@@ -33561,6 +33561,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
 @need 200
 @opindex msha512
 @itemx -msha512
+@need 200
+@opindex msm4
+@itemx -msm4
 These switches enable the use of instructions in the MMX, SSE,
 AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
 AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -33571,8 +33574,8 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
 ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
 UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
 AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512 or CLDEMOTE extended instruction sets.
-Each has a corresponding @option{-mno-} option to disable use of these
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4 or CLDEMOTE extended instruction
+sets. Each has a corresponding @option{-mno-} option to disable use of these
 instructions.
 
 These extensions are also available as built-in functions: see
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 54a062d..e5d15d6 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2595,6 +2595,9 @@ Target supports the execution of @code{sha512} instructions.
 @item sm3
 Target supports the execution of @code{sm3} instructions.
 
+@item sm4
+Target supports the execution of @code{sm4} instructions.
+
 @item sqrt_insn
 Target has a square root instruction that the compiler can generate.