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| author | Venkataramanan Kumar <venkataramanan.kumar@amd.com> | 2012-03-01 09:57:59 +0000 |
|---|---|---|
| committer | Venkataramanan Kumar <vekumar@gcc.gnu.org> | 2012-03-01 09:57:59 +0000 |
| commit | 283b529696df97afe8ce08b14c6d62c42b7f1d28 (patch) | |
| tree | cf2c20e9a82d7a14ca748e1a988a883b5ff4d392 /gcc/doc | |
| parent | bedcedc1268738d912e7ad12feb5f2f90d153a38 (diff) | |
| download | gcc-283b529696df97afe8ce08b14c6d62c42b7f1d28.zip gcc-283b529696df97afe8ce08b14c6d62c42b7f1d28.tar.gz gcc-283b529696df97afe8ce08b14c6d62c42b7f1d28.tar.bz2 | |
Document AMD bdver2 in invoke.texi
From-SVN: r184688
Diffstat (limited to 'gcc/doc')
| -rw-r--r-- | gcc/doc/invoke.texi | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e57f586..b806eb4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -13084,8 +13084,12 @@ instruction set extensions.) @item bdver1 AMD Family 15h core based CPUs with x86-64 instruction set support. (This supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, -SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit -instruction set extensions.) +SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) +@item bdver2 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set +extensions.) @item btver1 AMD Family 14h core based CPUs with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit |